ASoC: dt-bindings: mediatek,mt8188-afe: add audio afe document
Add mt8188 audio afe document. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230116034131.23943-11-trevor.wu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Trevor Wu
Mark Brown
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek AFE PCM controller for mt8188
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maintainers:
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- Trevor Wu <trevor.wu@mediatek.com>
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properties:
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compatible:
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const: mediatek,mt8188-afe
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: audiosys
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mediatek,topckgen:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: The phandle of the mediatek topckgen controller
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: 26M clock
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- description: audio pll1 clock
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- description: audio pll2 clock
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- description: clock divider for i2si1_mck
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- description: clock divider for i2si2_mck
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- description: clock divider for i2so1_mck
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- description: clock divider for i2so2_mck
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- description: clock divider for dptx_mck
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- description: a1sys hoping clock
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- description: audio intbus clock
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- description: audio hires clock
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- description: audio local bus clock
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- description: mux for dptx_mck
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- description: mux for i2so1_mck
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- description: mux for i2so2_mck
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- description: mux for i2si1_mck
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- description: mux for i2si2_mck
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- description: audio 26m clock
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clock-names:
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items:
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- const: clk26m
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- const: apll1
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- const: apll2
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- const: apll12_div0
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- const: apll12_div1
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- const: apll12_div2
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- const: apll12_div3
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- const: apll12_div9
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- const: a1sys_hp_sel
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- const: aud_intbus_sel
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- const: audio_h_sel
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- const: audio_local_bus_sel
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- const: dptx_m_sel
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- const: i2so1_m_sel
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- const: i2so2_m_sel
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- const: i2si1_m_sel
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- const: i2si2_m_sel
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- const: adsp_audio_26m
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mediatek,etdm-in1-cowork-source:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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etdm modules can share the same external clock pin. Specify
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which etdm clock source is required by this etdm in module.
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enum:
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- 1 # etdm2_in
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- 2 # etdm1_out
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- 3 # etdm2_out
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mediatek,etdm-in2-cowork-source:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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etdm modules can share the same external clock pin. Specify
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which etdm clock source is required by this etdm in module.
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enum:
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- 0 # etdm1_in
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- 2 # etdm1_out
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- 3 # etdm2_out
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mediatek,etdm-out1-cowork-source:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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etdm modules can share the same external clock pin. Specify
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which etdm clock source is required by this etdm out module.
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enum:
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- 0 # etdm1_in
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- 1 # etdm2_in
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- 3 # etdm2_out
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mediatek,etdm-out2-cowork-source:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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etdm modules can share the same external clock pin. Specify
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which etdm clock source is required by this etdm out module.
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enum:
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- 0 # etdm1_in
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- 1 # etdm2_in
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- 2 # etdm1_out
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patternProperties:
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"^mediatek,etdm-in[1-2]-chn-disabled$":
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$ref: /schemas/types.yaml#/definitions/uint8-array
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minItems: 1
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maxItems: 16
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description:
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This is a list of channel IDs which should be disabled.
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By default, all data received from ETDM pins will be outputed to
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memory. etdm in supports disable_out in direct mode(w/o interconn),
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so user can disable the specified channels by the property.
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uniqueItems: true
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items:
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minimum: 0
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maximum: 15
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"^mediatek,etdm-in[1-2]-multi-pin-mode$":
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type: boolean
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description: if present, the etdm data mode is I2S.
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"^mediatek,etdm-out[1-3]-multi-pin-mode$":
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type: boolean
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description: if present, the etdm data mode is I2S.
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required:
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- compatible
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- reg
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- interrupts
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- resets
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- reset-names
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- mediatek,topckgen
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- power-domains
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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afe@10b10000 {
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compatible = "mediatek,mt8188-afe";
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reg = <0x10b10000 0x10000>;
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interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
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resets = <&watchdog 14>;
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reset-names = "audiosys";
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mediatek,topckgen = <&topckgen>;
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power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO
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mediatek,etdm-in2-cowork-source = <2>;
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mediatek,etdm-out2-cowork-source = <0>;
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mediatek,etdm-in1-multi-pin-mode;
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mediatek,etdm-in1-chn-disabled = /bits/ 8 <0x0 0x2>;
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clocks = <&clk26m>,
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<&apmixedsys 9>, //CLK_APMIXED_APLL1
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<&apmixedsys 10>, //CLK_APMIXED_APLL2
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<&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0
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<&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1
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<&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2
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<&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3
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<&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9
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<&topckgen 83>, //CLK_TOP_A1SYS_HP
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<&topckgen 31>, //CLK_TOP_AUD_INTBUS
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<&topckgen 32>, //CLK_TOP_AUDIO_H
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<&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS
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<&topckgen 81>, //CLK_TOP_DPTX
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<&topckgen 77>, //CLK_TOP_I2SO1
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<&topckgen 78>, //CLK_TOP_I2SO2
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<&topckgen 79>, //CLK_TOP_I2SI1
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<&topckgen 80>, //CLK_TOP_I2SI2
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<&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M
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clock-names = "clk26m",
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"apll1",
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"apll2",
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"apll12_div0",
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"apll12_div1",
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"apll12_div2",
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"apll12_div3",
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"apll12_div9",
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"a1sys_hp_sel",
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"aud_intbus_sel",
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"audio_h_sel",
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"audio_local_bus_sel",
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"dptx_m_sel",
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"i2so1_m_sel",
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"i2so2_m_sel",
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"i2si1_m_sel",
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"i2si2_m_sel",
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"adsp_audio_26m";
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};
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...
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