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drm/bridge: ti-sn65dsi86: Fix output polarity setting bug
[ Upstream commit8c11586450
] According to the description in ti-sn65dsi86's datasheet: CHA_HSYNC_POLARITY: 0 = Active High Pulse. Synchronization signal is high for the sync pulse width. (default) 1 = Active Low Pulse. Synchronization signal is low for the sync pulse width. CHA_VSYNC_POLARITY: 0 = Active High Pulse. Synchronization signal is high for the sync pulse width. (Default) 1 = Active Low Pulse. Synchronization signal is low for the sync pulse width. We should only set these bits when the polarity is negative. Fixes:a095f15c00
("drm/bridge: add support for sn65dsi86 bridge driver") Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20221125104558.84616-1-eddy.zhang@rock-chips.com Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 2 additions and 2 deletions
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@ -906,9 +906,9 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
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&pdata->bridge.encoder->crtc->state->adjusted_mode;
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u8 hsync_polarity = 0, vsync_polarity = 0;
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if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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hsync_polarity = CHA_HSYNC_POLARITY;
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if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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vsync_polarity = CHA_VSYNC_POLARITY;
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ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
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