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synced 2024-08-20 14:16:02 +00:00
s3c2410fb: adds pixclock to s3c2410fb_display
This patch adds pixelclock field to the s3c2410fb_display structure and make use of it in the driver. The Bast machine defined 9 modes but pixclock and margin values are defined only for the 640x480 modes so I removed other modes. This patch also fixes wrong display type constant for the SMDK2440 board. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
parent
9fa7bc016a
commit
69816699fa
8 changed files with 28 additions and 136 deletions
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@ -174,6 +174,7 @@ static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
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.type = S3C2410_LCDCON1_STN4,
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.pixclock = 680000, /* HCLK = 100MHz */
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.xres = 160,
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.yres = 160,
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.bpp = 4,
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@ -473,25 +473,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
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.width = 640,
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.height = 480,
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.xres = 320,
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.yres = 240,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.bpp = 4,
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.lcdcon1 = 0x00000176,
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.lcdcon5 = 0x00014b02,
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},
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.pixclock = 33333,
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.xres = 640,
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.yres = 480,
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.bpp = 4,
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@ -510,42 +492,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
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.width = 640,
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.height = 480,
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.xres = 800,
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.yres = 600,
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.bpp = 4,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon1 = 0x00000176,
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.lcdcon5 = 0x00014b02,
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},
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.xres = 320,
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.yres = 240,
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.bpp = 8,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon1 = 0x00000176,
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.lcdcon5 = 0x00014b02,
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},
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.pixclock = 33333,
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.xres = 640,
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.yres = 480,
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.bpp = 8,
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@ -564,42 +511,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
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.width = 640,
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.height = 480,
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.xres = 800,
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.yres = 600,
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.bpp = 8,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon1 = 0x00000176,
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.lcdcon5 = 0x00014b02,
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},
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.xres = 320,
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.yres = 240,
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.bpp = 16,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon1 = 0x00000176,
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.lcdcon5 = 0x00014b02,
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},
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.pixclock = 33333,
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.xres = 640,
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.yres = 480,
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.bpp = 16,
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@ -610,24 +522,6 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon1 = 0x00000176,
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.lcdcon5 = 0x00014b02,
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},
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{
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.type = S3C2410_LCDCON1_TFT,
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.width = 640,
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.height = 480,
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.xres = 800,
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.yres = 600,
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.bpp = 16,
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.left_margin = 40,
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.right_margin = 20,
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.hsync_len = 88,
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.upper_margin = 30,
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.lower_margin = 32,
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.vsync_len = 3,
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.lcdcon1 = 0x00000176,
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.lcdcon5 = 0x00014b02,
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},
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@ -145,6 +145,7 @@ static struct s3c2410fb_display h1940_lcd __initdata = {
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.type = S3C2410_LCDCON1_TFT,
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.width = 240,
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.height = 320,
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.pixclock = 260000,
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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@ -112,6 +112,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
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.width = 640,
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.height = 480,
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.pixclock = 40000, /* HCLK/4 */
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.xres = 640,
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.yres = 480,
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.bpp = 16,
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@ -137,6 +138,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
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.type = S3C2410_LCDCON1_TFT,
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.width = 480,
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.height = 640,
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.pixclock = 40000, /* HCLK/4 */
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.xres = 480,
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.yres = 640,
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.bpp = 16,
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@ -162,6 +164,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
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.type = S3C2410_LCDCON1_TFT,
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.width = 240,
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.height = 320,
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.pixclock = 100000, /* HCLK/10 */
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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@ -123,6 +123,7 @@ static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
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.width = 240,
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.height = 320,
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.pixclock = 260000,
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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@ -115,11 +115,12 @@ static struct s3c2410fb_display smdk2440_lcd_cfg __initdata = {
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S3C2410_LCDCON5_PWREN |
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S3C2410_LCDCON5_HWSWP,
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.type = S3C2410_LCDCON1_TFT16BPP,
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.type = S3C2410_LCDCON1_TFT,
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.width = 240,
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.height = 320,
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.pixclock = 166667, /* HCLK 60 MHz, divisor 10 */
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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@ -199,6 +199,7 @@ static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
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var->width = display->width;
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/* copy lcd settings */
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var->pixclock = display->pixclock;
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var->left_margin = display->left_margin;
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var->right_margin = display->right_margin;
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var->upper_margin = display->upper_margin;
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@ -297,10 +298,6 @@ static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
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unsigned wdly = (var->left_margin >> 4) - 1;
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unsigned wlh = (var->hsync_len >> 4) - 1;
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dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
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dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
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dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
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if (type != S3C2410_LCDCON1_STN4)
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hs >>= 1;
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@ -359,10 +356,6 @@ static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
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const struct s3c2410fb_info *fbi = info->par;
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const struct fb_var_screeninfo *var = &info->var;
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dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
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dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
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dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
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regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
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switch (var->bits_per_pixel) {
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@ -427,28 +420,25 @@ static void s3c2410fb_activate_var(struct fb_info *info)
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void __iomem *regs = fbi->io;
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int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
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struct fb_var_screeninfo *var = &info->var;
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int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
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if (var->pixclock > 0) {
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int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
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dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
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dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
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dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
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if (type == S3C2410_LCDCON1_TFT) {
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clkdiv = (clkdiv / 2) - 1;
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if (clkdiv < 0)
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clkdiv = 0;
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} else {
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clkdiv = (clkdiv / 2);
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if (clkdiv < 2)
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clkdiv = 2;
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}
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fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
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fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
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if (type == S3C2410_LCDCON1_TFT) {
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s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
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--clkdiv;
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if (clkdiv < 0)
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clkdiv = 0;
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} else {
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s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
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if (clkdiv < 2)
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clkdiv = 2;
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}
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if (type == S3C2410_LCDCON1_TFT)
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s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
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else
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s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
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fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
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fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
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/* write new registers */
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@ -36,6 +36,7 @@ struct s3c2410fb_display {
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unsigned short yres;
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unsigned short bpp;
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unsigned pixclock; /* pixclock in picoseconds */
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unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
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unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
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unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
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