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spi_mpc83xx.c underclocking hotfix
The MPC83xx SPI controller clock divider can divide the system clock by not more then 1024. The spi_mpc83xx driver does not check this and silently writes garbage to the SPI controller registers when asked to run at lower frequencies. I've tried to run the SPI on a 266MHz MPC8349E with 100kHz for debugging a bus problem and suddenly was confronted with a 2nd problem to debug.. ;-) The patch adds an additional check which avoids writing garbage to the SPI controller registers and warn the user about it. This might help others to avoid simmilar problems. Cc: Kumar Gala <galak@gate.crashing.org> Cc: David Brownell <david-b@pacbell.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -158,6 +158,12 @@ static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
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if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
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u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
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if (pm > 0x0f) {
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printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
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"Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
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spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
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pm = 0x0f;
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}
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regval |= SPMODE_PM(pm) | SPMODE_DIV16;
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} else {
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u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
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