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clk: meson-axg: pcie: drop the mpll3 clock parent

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We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.

Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: Jianxin Qin <jianxin.qin@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Yixun Lan 2018-08-01 12:16:24 +00:00 committed by Jerome Brunet
parent 56dbabc0ff
commit 69b93104c7
1 changed files with 4 additions and 2 deletions
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6
drivers/clk/meson/axg.c
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@ -730,12 +730,14 @@ static struct clk_regmap axg_pcie_mux = {
.offset = HHI_PCIE_PLL_CNTL6,
.mask = 0x1,
.shift = 2,
/* skip the parent mpll3, reserved for debug */
.table = (u32[]){ 1 },
},
.hw.init = &(struct clk_init_data){
.name = "pcie_mux",
.ops = &clk_regmap_mux_ops,
.parent_names = (const char *[]){ "mpll3", "pcie_pll" },
.num_parents = 2,
.parent_names = (const char *[]){ "pcie_pll" },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};