reset: Create subdirectory for StarFive drivers
This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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@ -232,13 +232,6 @@ config RESET_SOCFPGA
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This enables the reset driver for the SoCFPGA ARMv7 platforms. This
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This enables the reset driver for the SoCFPGA ARMv7 platforms. This
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driver gets initialized early during platform init calls.
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driver gets initialized early during platform init calls.
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config RESET_STARFIVE_JH7100
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bool "StarFive JH7100 Reset Driver"
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depends on ARCH_STARFIVE || COMPILE_TEST
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default ARCH_STARFIVE
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help
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This enables the reset controller driver for the StarFive JH7100 SoC.
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config RESET_SUNPLUS
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config RESET_SUNPLUS
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bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
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bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
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default ARCH_SUNPLUS
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default ARCH_SUNPLUS
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@ -320,6 +313,7 @@ config RESET_ZYNQ
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help
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help
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This enables the reset controller driver for Xilinx Zynq SoCs.
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This enables the reset controller driver for Xilinx Zynq SoCs.
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source "drivers/reset/starfive/Kconfig"
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source "drivers/reset/sti/Kconfig"
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source "drivers/reset/sti/Kconfig"
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source "drivers/reset/hisilicon/Kconfig"
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source "drivers/reset/hisilicon/Kconfig"
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source "drivers/reset/tegra/Kconfig"
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source "drivers/reset/tegra/Kconfig"
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@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0
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obj-y += core.o
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obj-y += core.o
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obj-y += hisilicon/
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obj-y += hisilicon/
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obj-y += starfive/
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obj-$(CONFIG_ARCH_STI) += sti/
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obj-$(CONFIG_ARCH_STI) += sti/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
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obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
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@ -30,7 +31,6 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
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obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
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obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
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obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
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obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config RESET_STARFIVE_JH7100
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bool "StarFive JH7100 Reset Driver"
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depends on ARCH_STARFIVE || COMPILE_TEST
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default ARCH_STARFIVE
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help
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This enables the reset controller driver for the StarFive JH7100 SoC.
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@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
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