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net: bcmgenet: Use correct I/O accessors
The GENET driver currently uses __raw_{read,write}l which means native I/O endian. This works correctly for an ARM LE kernel (default) but fails miserably on an ARM BE (BE8) kernel where registers are kept little endian, so replace uses with {read,write}l_relaxed here which is what we want because this is all performance sensitive code. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
b6eb9d5000
commit
69d2ea9c79
2 changed files with 58 additions and 30 deletions
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@ -72,23 +72,42 @@
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#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
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TOTAL_DESC * DMA_DESC_SIZE)
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static inline void bcmgenet_writel(u32 value, void __iomem *offset)
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{
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/* MIPS chips strapped for BE will automagically configure the
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* peripheral registers for CPU-native byte order.
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*/
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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__raw_writel(value, offset);
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else
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writel_relaxed(value, offset);
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}
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static inline u32 bcmgenet_readl(void __iomem *offset)
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{
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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return __raw_readl(offset);
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else
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return readl_relaxed(offset);
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}
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static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
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void __iomem *d, u32 value)
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{
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__raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
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bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
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}
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static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
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void __iomem *d)
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{
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return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
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return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS);
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}
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static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
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void __iomem *d,
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dma_addr_t addr)
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{
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__raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
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bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
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/* Register writes to GISB bus can take couple hundred nanoseconds
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* and are done for each packet, save these expensive writes unless
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@ -96,7 +115,7 @@ static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
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*/
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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if (priv->hw_params->flags & GENET_HAS_40BITS)
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__raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
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bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
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#endif
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}
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@ -113,7 +132,7 @@ static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
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{
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dma_addr_t addr;
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addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
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addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
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/* Register writes to GISB bus can take couple hundred nanoseconds
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* and are done for each packet, save these expensive writes unless
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@ -121,7 +140,7 @@ static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
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*/
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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if (priv->hw_params->flags & GENET_HAS_40BITS)
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addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
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addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
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#endif
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return addr;
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}
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@ -156,8 +175,8 @@ static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
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if (GENET_IS_V1(priv))
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return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
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else
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return __raw_readl(priv->base +
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priv->hw_params->tbuf_offset + TBUF_CTRL);
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return bcmgenet_readl(priv->base +
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priv->hw_params->tbuf_offset + TBUF_CTRL);
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}
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static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
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@ -165,7 +184,7 @@ static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
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if (GENET_IS_V1(priv))
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bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
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else
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__raw_writel(val, priv->base +
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bcmgenet_writel(val, priv->base +
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priv->hw_params->tbuf_offset + TBUF_CTRL);
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}
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@ -174,8 +193,8 @@ static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
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if (GENET_IS_V1(priv))
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return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
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else
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return __raw_readl(priv->base +
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priv->hw_params->tbuf_offset + TBUF_BP_MC);
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return bcmgenet_readl(priv->base +
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priv->hw_params->tbuf_offset + TBUF_BP_MC);
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}
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static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
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@ -183,7 +202,7 @@ static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
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if (GENET_IS_V1(priv))
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bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
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else
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__raw_writel(val, priv->base +
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bcmgenet_writel(val, priv->base +
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priv->hw_params->tbuf_offset + TBUF_BP_MC);
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}
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@ -326,28 +345,28 @@ static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
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static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
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enum dma_reg r)
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{
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return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
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DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
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return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
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DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
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}
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static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
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u32 val, enum dma_reg r)
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{
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__raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
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bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
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DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
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}
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static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
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enum dma_reg r)
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{
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return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
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DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
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return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
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DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
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}
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static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
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u32 val, enum dma_reg r)
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{
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__raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
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bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
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DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
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}
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@ -418,16 +437,16 @@ static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
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unsigned int ring,
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enum dma_ring_reg r)
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{
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return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
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(DMA_RING_SIZE * ring) +
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genet_dma_ring_regs[r]);
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return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
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(DMA_RING_SIZE * ring) +
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genet_dma_ring_regs[r]);
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}
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static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
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unsigned int ring, u32 val,
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enum dma_ring_reg r)
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{
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__raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
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bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
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(DMA_RING_SIZE * ring) +
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genet_dma_ring_regs[r]);
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}
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@ -436,16 +455,16 @@ static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
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unsigned int ring,
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enum dma_ring_reg r)
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{
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return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
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(DMA_RING_SIZE * ring) +
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genet_dma_ring_regs[r]);
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return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
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(DMA_RING_SIZE * ring) +
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genet_dma_ring_regs[r]);
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}
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static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
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unsigned int ring, u32 val,
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enum dma_ring_reg r)
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{
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__raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
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bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
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(DMA_RING_SIZE * ring) +
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genet_dma_ring_regs[r]);
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}
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@ -991,12 +1010,12 @@ static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
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bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
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/* Enable EEE and switch to a 27Mhz clock automatically */
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reg = __raw_readl(priv->base + off);
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reg = bcmgenet_readl(priv->base + off);
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if (enable)
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reg |= TBUF_EEE_EN | TBUF_PM_EN;
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else
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reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
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__raw_writel(reg, priv->base + off);
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bcmgenet_writel(reg, priv->base + off);
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/* Do the same for thing for RBUF */
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reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
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@ -672,12 +672,21 @@ struct bcmgenet_priv {
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static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \
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u32 off) \
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{ \
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return __raw_readl(priv->base + offset + off); \
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/* MIPS chips strapped for BE will automagically configure the \
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* peripheral registers for CPU-native byte order. \
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*/ \
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
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return __raw_readl(priv->base + offset + off); \
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else \
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return readl_relaxed(priv->base + offset + off); \
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} \
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static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \
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u32 val, u32 off) \
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{ \
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__raw_writel(val, priv->base + offset + off); \
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \
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return __raw_writel(val, priv->base + offset + off); \
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else \
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writel_relaxed(val, priv->base + offset + off); \
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}
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GENET_IO_MACRO(ext, GENET_EXT_OFF);
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