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phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B mode
Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-5-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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1 changed files with 15 additions and 0 deletions
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@ -552,6 +552,8 @@ struct qmp_phy_cfg {
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/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
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const struct qmp_phy_cfg_tbls tbls;
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/* Additional sequence for HS Series B */
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const struct qmp_phy_cfg_tbls tbls_hs_b;
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/* clock ids to be requested */
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const char * const *clk_list;
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@ -585,6 +587,7 @@ struct qmp_ufs {
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struct reset_control *ufs_reset;
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struct phy *phy;
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u32 mode;
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};
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static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
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@ -848,6 +851,8 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
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static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
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{
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qmp_ufs_serdes_init(qmp, &cfg->tbls);
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if (qmp->mode == PHY_MODE_UFS_HS_B)
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qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
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qmp_ufs_lanes_init(qmp, &cfg->tbls);
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qmp_ufs_pcs_init(qmp, &cfg->tbls);
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}
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@ -1018,9 +1023,19 @@ static int qmp_ufs_disable(struct phy *phy)
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return qmp_ufs_exit(phy);
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}
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static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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{
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struct qmp_ufs *qmp = phy_get_drvdata(phy);
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qmp->mode = mode;
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return 0;
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}
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static const struct phy_ops qcom_qmp_ufs_phy_ops = {
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.power_on = qmp_ufs_enable,
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.power_off = qmp_ufs_disable,
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.set_mode = qmp_ufs_set_mode,
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.owner = THIS_MODULE,
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};
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