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crypto: hisilicon/sec - not need to enable sm4 extra mode at HW V3
[ Upstream commit f8a2652826
]
It is not need to enable sm4 extra mode in at HW V3. Here is fix it.
Signed-off-by: Kai Ye <yekai13@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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parent
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commit
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1 changed files with 5 additions and 3 deletions
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@ -443,9 +443,11 @@ static int sec_engine_init(struct hisi_qm *qm)
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writel(SEC_SAA_ENABLE, qm->io_base + SEC_SAA_EN_REG);
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/* Enable sm4 extra mode, as ctr/ecb */
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writel_relaxed(SEC_BD_ERR_CHK_EN0,
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qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
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/* HW V2 enable sm4 extra mode, as ctr/ecb */
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if (qm->ver < QM_HW_V3)
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writel_relaxed(SEC_BD_ERR_CHK_EN0,
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qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
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/* Enable sm4 xts mode multiple iv */
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writel_relaxed(SEC_BD_ERR_CHK_EN1,
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qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
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