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Merge branch 'for-next/neoverse-n1-stale-instr' into for-next/core
Neoverse-N1 cores with the 'COHERENT_ICACHE' feature may fetch stale instructions when software depends on prefetch-speculation-protection instead of explicit synchronization. [0] The workaround is to trap I-Cache maintenance and issue an inner-shareable TLBI. The affected cores have a Coherent I-Cache, so the I-Cache maintenance isn't necessary. The core tells user-space it can skip it with CTR_EL0.DIC. We also have to trap this register to hide the bit forcing DIC-aware user-space to perform the maintenance. To avoid trapping all cache-maintenance, this workaround depends on a firmware component that only traps I-cache maintenance from EL0 and performs the workaround. For user-space, the kernel's work is to trap CTR_EL0 to hide DIC, and produce a fake IminLine. EL3 traps the now-necessary I-Cache maintenance and performs the inner-shareable-TLBI that makes everything better. [0] https://developer.arm.com/docs/sden885747/latest/arm-neoverse-n1-mp050-software-developer-errata-notice * for-next/neoverse-n1-stale-instr: arm64: Silence clang warning on mismatched value/register sizes arm64: compat: Workaround Neoverse-N1 #1542419 for compat user-space arm64: Fake the IminLine size on systems affected by Neoverse-N1 #1542419 arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419
This commit is contained in:
commit
6a036afb55
7 changed files with 73 additions and 3 deletions
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@ -88,6 +88,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | MMU-500 | #841119,826419 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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@ -558,6 +558,22 @@ config ARM64_ERRATUM_1463225
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If unsure, say Y.
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config ARM64_ERRATUM_1542419
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bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
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default y
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help
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This option adds a workaround for ARM Neoverse-N1 erratum
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1542419.
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Affected Neoverse-N1 cores could execute a stale instruction when
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modified by another CPU. The workaround depends on a firmware
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counterpart.
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Workaround the issue by hiding the DIC feature from EL0. This
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forces user-space to perform cache maintenance.
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If unsure, say Y.
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config CAVIUM_ERRATUM_22375
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bool "Cavium erratum 22375, 24313"
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default y
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@ -11,6 +11,7 @@
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#define CTR_L1IP_MASK 3
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#define CTR_DMINLINE_SHIFT 16
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#define CTR_IMINLINE_SHIFT 0
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#define CTR_IMINLINE_MASK 0xf
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#define CTR_ERG_SHIFT 20
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#define CTR_CWG_SHIFT 24
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#define CTR_CWG_MASK 15
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@ -18,7 +19,7 @@
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#define CTR_DIC_SHIFT 29
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#define CTR_CACHE_MINLINE_MASK \
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(0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)
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(0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
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#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
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@ -54,7 +54,8 @@
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#define ARM64_WORKAROUND_1463225 44
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45
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#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46
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#define ARM64_WORKAROUND_1542419 47
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#define ARM64_NCAPS 47
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#define ARM64_NCAPS 48
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#endif /* __ASM_CPUCAPS_H */
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@ -88,13 +88,21 @@ has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
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}
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static void
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cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *__unused)
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cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
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{
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u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
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bool enable_uct_trap = false;
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/* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
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if ((read_cpuid_cachetype() & mask) !=
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(arm64_ftr_reg_ctrel0.sys_val & mask))
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enable_uct_trap = true;
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/* ... or if the system is affected by an erratum */
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if (cap->capability == ARM64_WORKAROUND_1542419)
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enable_uct_trap = true;
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if (enable_uct_trap)
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sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
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}
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@ -648,6 +656,18 @@ needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
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return false;
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}
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static bool __maybe_unused
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has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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u32 midr = read_cpuid_id();
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bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
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const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
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WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
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return is_midr_in_range(midr, &range) && has_dic;
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}
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#ifdef CONFIG_HARDEN_EL2_VECTORS
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static const struct midr_range arm64_harden_el2_vectors[] = {
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@ -889,6 +909,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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.capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
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ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_1542419
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{
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/* we depend on the firmware portion for correctness */
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.desc = "ARM erratum 1542419 (kernel portion)",
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.capability = ARM64_WORKAROUND_1542419,
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
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.matches = has_neoverse_n1_erratum_1542419,
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.cpu_enable = cpu_enable_trap_ctr_access,
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},
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#endif
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{
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}
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@ -8,6 +8,7 @@
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*/
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#include <linux/compat.h>
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#include <linux/cpufeature.h>
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#include <linux/personality.h>
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#include <linux/sched.h>
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#include <linux/sched/signal.h>
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@ -17,6 +18,7 @@
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#include <asm/cacheflush.h>
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#include <asm/system_misc.h>
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#include <asm/tlbflush.h>
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#include <asm/unistd.h>
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static long
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@ -30,6 +32,15 @@ __do_compat_cache_op(unsigned long start, unsigned long end)
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if (fatal_signal_pending(current))
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return 0;
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if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
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/*
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* The workaround requires an inner-shareable tlbi.
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* We pick the reserved-ASID to minimise the impact.
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*/
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__tlbi(aside1is, __TLBI_VADDR(0, 0));
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dsb(ish);
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}
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ret = __flush_cache_user_range(start, start + chunk);
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if (ret)
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return ret;
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@ -470,6 +470,15 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
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int rt = ESR_ELx_SYS64_ISS_RT(esr);
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unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0);
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if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) {
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/* Hide DIC so that we can trap the unnecessary maintenance...*/
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val &= ~BIT(CTR_DIC_SHIFT);
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/* ... and fake IminLine to reduce the number of traps. */
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val &= ~CTR_IMINLINE_MASK;
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val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK;
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}
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pt_regs_write_reg(regs, rt, val);
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arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
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