ARM: vexpress: Motherboard RS1 memory map support

This patch adds support for RS1 memory map based Versatile Express
motherboard.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
This commit is contained in:
Pawel Moll 2011-12-09 18:47:39 +00:00
parent 8deed1786a
commit 6a3719562b
4 changed files with 309 additions and 6 deletions

View file

@ -0,0 +1,201 @@
/*
* ARM Ltd. Versatile Express
*
* Motherboard Express uATX
* V2M-P1
*
* HBI-0190D
*
* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
* Technical Reference Manual)
*
* WARNING! The hardware described in this file is independent from the
* original variant (vexpress-v2m.dtsi), but there is a strong
* correspondence between the two configurations.
*
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
* CHANGES TO vexpress-v2m.dtsi!
*/
/ {
aliases {
arm,v2m_timer = &v2m_timer01;
};
motherboard {
compatible = "simple-bus";
arm,v2m-memory-map = "rs1";
#address-cells = <2>; /* SMB chipselect number and offset */
#size-cells = <1>;
#interrupt-cells = <1>;
flash@0,00000000 {
compatible = "arm,vexpress-flash", "cfi-flash";
reg = <0 0x00000000 0x04000000>,
<4 0x00000000 0x04000000>;
bank-width = <4>;
};
psram@1,00000000 {
compatible = "arm,vexpress-psram", "mtd-ram";
reg = <1 0x00000000 0x02000000>;
bank-width = <4>;
};
vram@2,00000000 {
compatible = "arm,vexpress-vram";
reg = <2 0x00000000 0x00800000>;
};
ethernet@2,02000000 {
compatible = "smsc,lan9118", "smsc,lan9115";
reg = <2 0x02000000 0x10000>;
interrupts = <15>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,irq-active-high;
smsc,irq-push-pull;
};
usb@2,03000000 {
compatible = "nxp,usb-isp1761";
reg = <2 0x03000000 0x20000>;
interrupts = <16>;
port1-otg;
};
iofpga@3,00000000 {
compatible = "arm,amba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 3 0 0x200000>;
sysreg@010000 {
compatible = "arm,vexpress-sysreg";
reg = <0x010000 0x1000>;
};
sysctl@020000 {
compatible = "arm,sp810", "arm,primecell";
reg = <0x020000 0x1000>;
};
/* PCI-E I2C bus */
v2m_i2c_pcie: i2c@030000 {
compatible = "arm,versatile-i2c";
reg = <0x030000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
pcie-switch@60 {
compatible = "idt,89hpes32h8";
reg = <0x60>;
};
};
aaci@040000 {
compatible = "arm,pl041", "arm,primecell";
reg = <0x040000 0x1000>;
interrupts = <11>;
};
mmci@050000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>;
interrupts = <9 10>;
};
kmi@060000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>;
interrupts = <12>;
};
kmi@070000 {
compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>;
interrupts = <13>;
};
v2m_serial0: uart@090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>;
interrupts = <5>;
};
v2m_serial1: uart@0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>;
interrupts = <6>;
};
v2m_serial2: uart@0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>;
interrupts = <7>;
};
v2m_serial3: uart@0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>;
interrupts = <8>;
};
wdt@0f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x1000>;
interrupts = <0>;
};
v2m_timer01: timer@110000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x1000>;
interrupts = <2>;
};
v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x1000>;
};
/* DVI I2C bus */
v2m_i2c_dvi: i2c@160000 {
compatible = "arm,versatile-i2c";
reg = <0x160000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
dvi-transmitter@39 {
compatible = "sil,sii9022-tpi", "sil,sii9022";
reg = <0x39>;
};
dvi-transmitter@60 {
compatible = "sil,sii9022-cpi", "sil,sii9022";
reg = <0x60>;
};
};
rtc@170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x1000>;
interrupts = <4>;
};
compact-flash@1a0000 {
compatible = "arm,vexpress-cf", "ata-generic";
reg = <0x1a0000 0x100
0x1a0100 0xf00>;
reg-shift = <2>;
};
clcd@1f0000 {
compatible = "arm,pl111", "arm,primecell";
reg = <0x1f0000 0x1000>;
interrupts = <14>;
};
};
};
};

View file

@ -10,12 +10,34 @@
* published by the Free Software Foundation.
*/
#define DEBUG_LL_UART_OFFSET 0x00009000
#define DEBUG_LL_PHYS_BASE 0x10000000
#define DEBUG_LL_UART_OFFSET 0x00009000
#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
#define DEBUG_LL_VIRT_BASE 0xf8000000
.macro addruart,rp,rv,tmp
mov \rp, #DEBUG_LL_UART_OFFSET
orr \rv, \rp, #0xf8000000 @ virtual base
orr \rp, \rp, #0x10000000 @ physical base
@ Make an educated guess regarding the memory map:
@ - the original A9 core tile, which has MPCore peripherals
@ located at 0x1e000000, should use UART at 0x10009000
@ - all other (RS1 complaint) tiles use UART mapped
@ at 0x1c090000
mrc p15, 4, \tmp, c15, c0, 0
cmp \tmp, #0x1e000000
@ Original memory map
moveq \rp, #DEBUG_LL_UART_OFFSET
orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
@ RS1 memory map
movne \rp, #DEBUG_LL_UART_OFFSET_RS1
orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
.endm
#include <asm/hardware/debug-pl01x.S>

View file

@ -22,7 +22,27 @@
#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
#define get_uart_base() (0x10000000 + 0x00009000)
#define UART_BASE 0x10009000
#define UART_BASE_RS1 0x1c090000
static unsigned long get_uart_base(void)
{
unsigned long mpcore_periph;
/*
* Make an educated guess regarding the memory map:
* - the original A9 core tile, which has MPCore peripherals
* located at 0x1e000000, should use UART at 0x10009000
* - all other (RS1 complaint) tiles use UART mapped
* at 0x1c090000
*/
asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
if (mpcore_periph == 0x1e000000)
return UART_BASE;
else
return UART_BASE_RS1;
}
/*
* This does not append a newline

View file

@ -486,9 +486,36 @@ MACHINE_END
#if defined(CONFIG_ARCH_VEXPRESS_DT)
static struct map_desc v2m_rs1_io_desc __initdata = {
.virtual = V2M_PERIPH,
.pfn = __phys_to_pfn(0x1c000000),
.length = SZ_2M,
.type = MT_DEVICE,
};
static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
int depth, void *data)
{
const char **map = data;
if (strcmp(uname, "motherboard") != 0)
return 0;
*map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
return 1;
}
void __init v2m_dt_map_io(void)
{
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
const char *map = NULL;
of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
if (map && strcmp(map, "rs1") == 0)
iotable_init(&v2m_rs1_io_desc, 1);
else
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
#if defined(CONFIG_SMP)
vexpress_dt_smp_map_io();
@ -535,6 +562,35 @@ static struct clk_lookup v2m_dt_lookups[] = {
.dev_id = "1001f000.clcd",
.clk = &osc1_clk,
},
/* RS1 memory map */
{ /* PL180 MMCI */
.dev_id = "mb:mmci", /* 1c050000.mmci */
.clk = &osc2_clk,
}, { /* PL050 KMI0 */
.dev_id = "1c060000.kmi",
.clk = &osc2_clk,
}, { /* PL050 KMI1 */
.dev_id = "1c070000.kmi",
.clk = &osc2_clk,
}, { /* PL011 UART0 */
.dev_id = "1c090000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART1 */
.dev_id = "1c0a0000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART2 */
.dev_id = "1c0b0000.uart",
.clk = &osc2_clk,
}, { /* PL011 UART3 */
.dev_id = "1c0c0000.uart",
.clk = &osc2_clk,
}, { /* SP805 WDT */
.dev_id = "1c0f0000.wdt",
.clk = &v2m_ref_clk,
}, { /* PL111 CLCD */
.dev_id = "1c1f0000.clcd",
.clk = &osc1_clk,
},
};
void __init v2m_dt_init_early(void)
@ -597,6 +653,10 @@ static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
&v2m_flash_data),
OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
/* RS1 memory map */
OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
&v2m_flash_data),
OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
{}
};