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PCI: imx6: Simplify clock handling by using clk_bulk*() function
Refactor the clock handling logic. Add 'clk_names' define in drvdata. Use clk_bulk*() API to simplify the code. Link: https://lore.kernel.org/r/20240220161924.3871774-2-Frank.Li@nxp.com Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Frank Li
Lorenzo Pieralisi
parent
9266514689
commit
6a40185838
1 changed files with 50 additions and 88 deletions
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@ -61,12 +61,16 @@ enum imx6_pcie_variants {
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#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
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#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
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#define IMX6_PCIE_MAX_CLKS 6
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struct imx6_pcie_drvdata {
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enum imx6_pcie_variants variant;
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enum dw_pcie_device_mode mode;
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u32 flags;
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int dbi_length;
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const char *gpr;
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const char * const *clk_names;
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const u32 clks_cnt;
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};
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struct imx6_pcie {
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@ -74,11 +78,7 @@ struct imx6_pcie {
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int reset_gpio;
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bool gpio_active_high;
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bool link_is_up;
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struct clk *pcie_bus;
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struct clk *pcie_phy;
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struct clk *pcie_inbound_axi;
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struct clk *pcie;
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struct clk *pcie_aux;
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struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS];
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struct regmap *iomuxc_gpr;
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u16 msi_ctrl;
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u32 controller_id;
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@ -407,13 +407,18 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
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static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
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{
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unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
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unsigned long phy_rate = 0;
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int mult, div;
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u16 val;
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int i;
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if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
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return 0;
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for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
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if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0)
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phy_rate = clk_get_rate(imx6_pcie->clks[i].clk);
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switch (phy_rate) {
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case 125000000:
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/*
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@ -550,19 +555,11 @@ static int imx6_pcie_attach_pd(struct device *dev)
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static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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struct device *dev = pci->dev;
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unsigned int offset;
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int ret = 0;
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switch (imx6_pcie->drvdata->variant) {
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case IMX6SX:
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ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
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if (ret) {
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dev_err(dev, "unable to enable pcie_axi clock\n");
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break;
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}
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
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break;
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@ -589,12 +586,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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case IMX8MQ_EP:
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case IMX8MP:
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case IMX8MP_EP:
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ret = clk_prepare_enable(imx6_pcie->pcie_aux);
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if (ret) {
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dev_err(dev, "unable to enable pcie_aux clock\n");
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break;
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}
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offset = imx6_pcie_grp_offset(imx6_pcie);
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/*
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* Set the over ride low and enabled
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@ -615,9 +606,6 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
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{
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switch (imx6_pcie->drvdata->variant) {
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case IMX6SX:
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clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
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break;
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case IMX6QP:
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case IMX6Q:
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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@ -631,14 +619,6 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
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break;
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case IMX8MM:
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case IMX8MM_EP:
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case IMX8MQ:
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case IMX8MQ_EP:
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case IMX8MP:
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case IMX8MP_EP:
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clk_disable_unprepare(imx6_pcie->pcie_aux);
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break;
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default:
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break;
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}
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@ -650,23 +630,9 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
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struct device *dev = pci->dev;
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int ret;
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ret = clk_prepare_enable(imx6_pcie->pcie_phy);
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if (ret) {
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dev_err(dev, "unable to enable pcie_phy clock\n");
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ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
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if (ret)
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return ret;
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}
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ret = clk_prepare_enable(imx6_pcie->pcie_bus);
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if (ret) {
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dev_err(dev, "unable to enable pcie_bus clock\n");
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goto err_pcie_bus;
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}
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ret = clk_prepare_enable(imx6_pcie->pcie);
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if (ret) {
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dev_err(dev, "unable to enable pcie clock\n");
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goto err_pcie;
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}
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ret = imx6_pcie_enable_ref_clk(imx6_pcie);
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if (ret) {
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@ -679,11 +645,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
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return 0;
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err_ref_clk:
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clk_disable_unprepare(imx6_pcie->pcie);
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err_pcie:
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clk_disable_unprepare(imx6_pcie->pcie_bus);
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err_pcie_bus:
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clk_disable_unprepare(imx6_pcie->pcie_phy);
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clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
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return ret;
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}
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@ -691,9 +653,7 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
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static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
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{
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imx6_pcie_disable_ref_clk(imx6_pcie);
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clk_disable_unprepare(imx6_pcie->pcie);
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clk_disable_unprepare(imx6_pcie->pcie_bus);
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clk_disable_unprepare(imx6_pcie->pcie_phy);
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clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
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}
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static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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@ -1252,6 +1212,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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struct device_node *node = dev->of_node;
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int ret;
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u16 val;
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int i;
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imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
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if (!imx6_pcie)
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@ -1305,32 +1266,20 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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return imx6_pcie->reset_gpio;
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}
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/* Fetch clocks */
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imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
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if (IS_ERR(imx6_pcie->pcie_bus))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
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"pcie_bus clock source missing or invalid\n");
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if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS)
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return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n");
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imx6_pcie->pcie = devm_clk_get(dev, "pcie");
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if (IS_ERR(imx6_pcie->pcie))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
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"pcie clock source missing or invalid\n");
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for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++)
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imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i];
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/* Fetch clocks */
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ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks);
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if (ret)
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return ret;
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switch (imx6_pcie->drvdata->variant) {
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case IMX6SX:
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imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
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"pcie_inbound_axi");
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if (IS_ERR(imx6_pcie->pcie_inbound_axi))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
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"pcie_inbound_axi clock missing or invalid\n");
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break;
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case IMX8MQ:
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case IMX8MQ_EP:
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imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
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if (IS_ERR(imx6_pcie->pcie_aux))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
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"pcie_aux clock source missing or invalid\n");
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fallthrough;
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case IMX7D:
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if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
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imx6_pcie->controller_id = 1;
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@ -1353,10 +1302,6 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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case IMX8MM_EP:
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case IMX8MP:
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case IMX8MP_EP:
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imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
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if (IS_ERR(imx6_pcie->pcie_aux))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
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"pcie_aux clock source missing or invalid\n");
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imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
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"apps");
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if (IS_ERR(imx6_pcie->apps_reset))
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@ -1372,14 +1317,6 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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default:
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break;
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}
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/* Don't fetch the pcie_phy clock, if it has abstract PHY driver */
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if (imx6_pcie->phy == NULL) {
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imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
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if (IS_ERR(imx6_pcie->pcie_phy))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
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"pcie_phy clock source missing or invalid\n");
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}
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/* Grab turnoff reset */
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imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
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@ -1470,6 +1407,11 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
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imx6_pcie_assert_core_reset(imx6_pcie);
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}
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static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"};
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static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"};
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static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"};
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static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"};
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static const struct imx6_pcie_drvdata drvdata[] = {
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[IMX6Q] = {
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.variant = IMX6Q,
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@ -1477,6 +1419,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
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.dbi_length = 0x200,
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.gpr = "fsl,imx6q-iomuxc-gpr",
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.clk_names = imx6q_clks,
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.clks_cnt = ARRAY_SIZE(imx6q_clks),
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},
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[IMX6SX] = {
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.variant = IMX6SX,
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@ -1484,6 +1428,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
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IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.gpr = "fsl,imx6q-iomuxc-gpr",
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.clk_names = imx6sx_clks,
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.clks_cnt = ARRAY_SIZE(imx6sx_clks),
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},
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[IMX6QP] = {
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.variant = IMX6QP,
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@ -1492,40 +1438,56 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.dbi_length = 0x200,
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.gpr = "fsl,imx6q-iomuxc-gpr",
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.clk_names = imx6q_clks,
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.clks_cnt = ARRAY_SIZE(imx6q_clks),
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},
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[IMX7D] = {
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.variant = IMX7D,
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.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.gpr = "fsl,imx7d-iomuxc-gpr",
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.clk_names = imx6q_clks,
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.clks_cnt = ARRAY_SIZE(imx6q_clks),
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},
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[IMX8MQ] = {
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.variant = IMX8MQ,
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.gpr = "fsl,imx8mq-iomuxc-gpr",
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.clk_names = imx8mq_clks,
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.clks_cnt = ARRAY_SIZE(imx8mq_clks),
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},
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[IMX8MM] = {
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.variant = IMX8MM,
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.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.gpr = "fsl,imx8mm-iomuxc-gpr",
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.clk_names = imx8mm_clks,
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.clks_cnt = ARRAY_SIZE(imx8mm_clks),
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},
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[IMX8MP] = {
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.variant = IMX8MP,
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.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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.gpr = "fsl,imx8mp-iomuxc-gpr",
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.clk_names = imx8mm_clks,
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.clks_cnt = ARRAY_SIZE(imx8mm_clks),
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},
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[IMX8MQ_EP] = {
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.variant = IMX8MQ_EP,
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.mode = DW_PCIE_EP_TYPE,
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.gpr = "fsl,imx8mq-iomuxc-gpr",
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.clk_names = imx8mq_clks,
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.clks_cnt = ARRAY_SIZE(imx8mq_clks),
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},
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[IMX8MM_EP] = {
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.variant = IMX8MM_EP,
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.mode = DW_PCIE_EP_TYPE,
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.gpr = "fsl,imx8mm-iomuxc-gpr",
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.clk_names = imx8mm_clks,
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.clks_cnt = ARRAY_SIZE(imx8mm_clks),
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},
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[IMX8MP_EP] = {
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.variant = IMX8MP_EP,
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.mode = DW_PCIE_EP_TYPE,
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.gpr = "fsl,imx8mp-iomuxc-gpr",
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.clk_names = imx8mm_clks,
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.clks_cnt = ARRAY_SIZE(imx8mm_clks),
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},
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};
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