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drm/i915: Clean up PIPECONF bit defines
Use REG_BIT() & co. for PIPECONF bits, and adjust the naming of various bits to be more consistent. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
parent
7e31ce581b
commit
6a6d914de3
6 changed files with 89 additions and 98 deletions
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@ -1051,7 +1051,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
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/* wait for transcoder to be enabled */
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if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
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I965_PIPECONF_ACTIVE, 10))
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PIPECONF_STATE_ENABLE, 10))
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drm_err(&dev_priv->drm,
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"DSI transcoder not enabled\n");
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}
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@ -1319,7 +1319,7 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
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/* wait for transcoder to be disabled */
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if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
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I965_PIPECONF_ACTIVE, 50))
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PIPECONF_STATE_ENABLE, 50))
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drm_err(&dev_priv->drm,
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"DSI trancoder not disabled\n");
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}
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@ -391,13 +391,11 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
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if (DISPLAY_VER(dev_priv) >= 4) {
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enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
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i915_reg_t reg = PIPECONF(cpu_transcoder);
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/* Wait for the Pipe State to go off */
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if (intel_de_wait_for_clear(dev_priv, reg,
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I965_PIPECONF_ACTIVE, 100))
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drm_WARN(&dev_priv->drm, 1,
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"pipe_off wait timed out\n");
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if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
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PIPECONF_STATE_ENABLE, 100))
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drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
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} else {
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intel_wait_for_pipe_scanline_stopped(crtc);
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}
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@ -3378,13 +3376,13 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
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switch (crtc_state->pipe_bpp) {
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case 18:
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pipeconf |= PIPECONF_6BPC;
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pipeconf |= PIPECONF_BPC_6;
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break;
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case 24:
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pipeconf |= PIPECONF_8BPC;
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pipeconf |= PIPECONF_BPC_8;
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break;
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case 30:
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pipeconf |= PIPECONF_10BPC;
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pipeconf |= PIPECONF_BPC_10;
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break;
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default:
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/* Case prevented by intel_choose_pipe_bpp_dither. */
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@ -3399,7 +3397,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
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else
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pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
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} else {
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pipeconf |= PIPECONF_PROGRESSIVE;
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pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
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}
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if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
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@ -3577,16 +3575,17 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
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IS_CHERRYVIEW(dev_priv)) {
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switch (tmp & PIPECONF_BPC_MASK) {
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case PIPECONF_6BPC:
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case PIPECONF_BPC_6:
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pipe_config->pipe_bpp = 18;
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break;
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case PIPECONF_8BPC:
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case PIPECONF_BPC_8:
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pipe_config->pipe_bpp = 24;
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break;
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case PIPECONF_10BPC:
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case PIPECONF_BPC_10:
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pipe_config->pipe_bpp = 30;
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break;
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default:
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MISSING_CASE(tmp);
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break;
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}
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}
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@ -3595,8 +3594,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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(tmp & PIPECONF_COLOR_RANGE_SELECT))
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pipe_config->limited_color_range = true;
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pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
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PIPECONF_GAMMA_MODE_SHIFT;
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pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
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if (IS_CHERRYVIEW(dev_priv))
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pipe_config->cgm_mode = intel_de_read(dev_priv,
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@ -3683,16 +3681,16 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
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switch (crtc_state->pipe_bpp) {
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case 18:
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val |= PIPECONF_6BPC;
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val |= PIPECONF_BPC_6;
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break;
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case 24:
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val |= PIPECONF_8BPC;
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val |= PIPECONF_BPC_8;
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break;
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case 30:
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val |= PIPECONF_10BPC;
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val |= PIPECONF_BPC_10;
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break;
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case 36:
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val |= PIPECONF_12BPC;
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val |= PIPECONF_BPC_12;
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break;
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default:
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/* Case prevented by intel_choose_pipe_bpp_dither. */
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@ -3700,12 +3698,12 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
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}
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if (crtc_state->dither)
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
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if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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val |= PIPECONF_INTERLACED_ILK;
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val |= PIPECONF_INTERLACE_IF_ID_ILK;
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else
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val |= PIPECONF_PROGRESSIVE;
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val |= PIPECONF_INTERLACE_PF_PD_ILK;
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/*
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* This would end up with an odd purple hue over
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@ -3737,12 +3735,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
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u32 val = 0;
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if (IS_HASWELL(dev_priv) && crtc_state->dither)
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val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
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val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
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if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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val |= PIPECONF_INTERLACED_ILK;
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val |= PIPECONF_INTERLACE_IF_ID_ILK;
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else
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val |= PIPECONF_PROGRESSIVE;
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val |= PIPECONF_INTERLACE_PF_PD_ILK;
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if (IS_HASWELL(dev_priv) &&
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crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
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@ -4036,16 +4034,16 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
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goto out;
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switch (tmp & PIPECONF_BPC_MASK) {
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case PIPECONF_6BPC:
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case PIPECONF_BPC_6:
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pipe_config->pipe_bpp = 18;
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break;
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case PIPECONF_8BPC:
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case PIPECONF_BPC_8:
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pipe_config->pipe_bpp = 24;
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break;
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case PIPECONF_10BPC:
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case PIPECONF_BPC_10:
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pipe_config->pipe_bpp = 30;
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break;
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case PIPECONF_12BPC:
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case PIPECONF_BPC_12:
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pipe_config->pipe_bpp = 36;
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break;
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default:
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@ -4065,8 +4063,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
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break;
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}
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pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
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PIPECONF_GAMMA_MODE_SHIFT;
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pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
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pipe_config->csc_mode = intel_de_read(dev_priv,
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PIPE_CSC_MODE(crtc->pipe));
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@ -10008,8 +10005,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
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udelay(150); /* wait for warmup */
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}
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intel_de_write(dev_priv, PIPECONF(pipe),
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PIPECONF_ENABLE | PIPECONF_PROGRESSIVE);
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intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
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intel_de_posting_read(dev_priv, PIPECONF(pipe));
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intel_wait_for_pipe_scanline_moving(crtc);
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@ -157,13 +157,13 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
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*/
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val &= ~PIPECONF_BPC_MASK;
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if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
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val |= PIPECONF_8BPC;
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val |= PIPECONF_BPC_8;
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else
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val |= pipeconf_val & PIPECONF_BPC_MASK;
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}
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val &= ~TRANS_INTERLACE_MASK;
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if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) {
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if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
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if (HAS_PCH_IBX(dev_priv) &&
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intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
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val |= TRANS_LEGACY_INTERLACED_ILK;
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@ -436,8 +436,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
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val = TRANS_ENABLE;
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pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
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if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
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PIPECONF_INTERLACED_ILK)
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if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
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val |= TRANS_INTERLACED;
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else
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val |= TRANS_PROGRESSIVE;
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@ -184,7 +184,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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for_each_pipe(dev_priv, pipe) {
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vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
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~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
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~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
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vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
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vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
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vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
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@ -245,7 +245,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
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* setup_virtual_dp_monitor.
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*/
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vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
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vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
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vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
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/*
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* Golden M/N are calculated based on:
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@ -702,11 +702,11 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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data = vgpu_vreg(vgpu, offset);
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if (data & PIPECONF_ENABLE) {
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vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
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vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE;
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vgpu_update_refresh_rate(vgpu);
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vgpu_update_vblank_emulation(vgpu, true);
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} else {
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vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
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vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE;
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vgpu_update_vblank_emulation(vgpu, false);
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}
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return 0;
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@ -5168,62 +5168,58 @@ enum {
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#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
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#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
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#define _PIPEACONF 0x70008
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#define PIPECONF_ENABLE (1 << 31)
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#define PIPECONF_DISABLE 0
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#define PIPECONF_DOUBLE_WIDE (1 << 30)
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#define I965_PIPECONF_ACTIVE (1 << 30)
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#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
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#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
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#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
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#define PIPECONF_SINGLE_WIDE 0
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#define PIPECONF_PIPE_UNLOCKED 0
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#define PIPECONF_PIPE_LOCKED (1 << 25)
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#define PIPECONF_FORCE_BORDER (1 << 25)
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#define PIPECONF_GAMMA_MODE_MASK_I9XX (1 << 24) /* gmch */
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#define PIPECONF_GAMMA_MODE_MASK_ILK (3 << 24) /* ilk-ivb */
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#define PIPECONF_GAMMA_MODE_8BIT (0 << 24) /* gmch,ilk-ivb */
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#define PIPECONF_GAMMA_MODE_10BIT (1 << 24) /* gmch,ilk-ivb */
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#define PIPECONF_GAMMA_MODE_12BIT (2 << 24) /* ilk-ivb */
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#define PIPECONF_GAMMA_MODE_SPLIT (3 << 24) /* ivb */
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#define PIPECONF_GAMMA_MODE(x) ((x) << 24) /* pass in GAMMA_MODE_MODE_* */
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#define PIPECONF_GAMMA_MODE_SHIFT 24
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#define PIPECONF_INTERLACE_MASK (7 << 21)
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#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
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/* Note that pre-gen3 does not support interlaced display directly. Panel
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* fitting must be disabled on pre-ilk for interlaced. */
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#define PIPECONF_PROGRESSIVE (0 << 21)
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#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
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#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
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#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
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#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
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/* Ironlake and later have a complete new set of values for interlaced. PFIT
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* means panel fitter required, PF means progressive fetch, DBL means power
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* saving pixel doubling. */
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#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
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#define PIPECONF_INTERLACED_ILK (3 << 21)
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#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
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#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
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#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
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#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
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#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
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#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
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#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
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#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
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#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
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#define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
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#define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
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#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
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#define PIPECONF_BPC_MASK (0x7 << 5)
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#define PIPECONF_8BPC (0 << 5)
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#define PIPECONF_10BPC (1 << 5)
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#define PIPECONF_6BPC (2 << 5)
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#define PIPECONF_12BPC (3 << 5)
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#define PIPECONF_DITHER_EN (1 << 4)
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#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
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#define PIPECONF_DITHER_TYPE_SP (0 << 2)
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#define PIPECONF_DITHER_TYPE_ST1 (1 << 2)
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#define PIPECONF_DITHER_TYPE_ST2 (2 << 2)
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#define PIPECONF_DITHER_TYPE_TEMP (3 << 2)
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#define PIPECONF_ENABLE REG_BIT(31)
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#define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
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#define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
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#define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
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#define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
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#define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
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#define PIPECONF_PIPE_LOCKED REG_BIT(25)
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#define PIPECONF_FORCE_BORDER REG_BIT(25)
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#define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
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#define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
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#define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
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#define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
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#define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
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#define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
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#define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
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#define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
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#define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
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#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
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#define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
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#define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
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#define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
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/*
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* ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
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* DBL=power saving pixel doubling, PF-ID* requires panel fitter
|
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*/
|
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#define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
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#define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
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#define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
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#define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
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#define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
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#define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
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#define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
|
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#define PIPECONF_EDP_RR_MODE_SWITCH REG_BIT(20)
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#define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
|
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#define PIPECONF_EDP_RR_MODE_SWITCH_VLV REG_BIT(14)
|
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#define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
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#define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
|
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#define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
|
||||
#define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
|
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#define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
|
||||
#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
|
||||
#define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
|
||||
#define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
|
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#define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
|
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#define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
|
||||
#define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
|
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#define PIPECONF_DITHER_EN REG_BIT(4)
|
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#define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
|
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#define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
|
||||
#define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
|
||||
#define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
|
||||
#define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
|
||||
#define _PIPEASTAT 0x70024
|
||||
#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
|
||||
#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
|
||||
|
|
Loading…
Reference in a new issue