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drm/i915: Kill intel_prepare_ddi()
Move the ddi buffer translation programming to occur from the encoder .pre_enable() hook, for just the ddi port we are enabling. Previously we used to reprogram the translations for all ddi ports during init and during power well enabling. v2: s/intel_prepare_ddi_buffers/intel_prepare_ddi_buffer/ (Daniel) Resolve conflicts due to dev_priv->atomic_cdclk_freq Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
10afa0b65f
commit
6a7e4f9989
6 changed files with 31 additions and 88 deletions
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@ -1077,7 +1077,6 @@ static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
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*/
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broxton_init_cdclk(dev);
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broxton_ddi_phy_init(dev);
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intel_prepare_ddi(dev);
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return 0;
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}
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@ -342,12 +342,6 @@ enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
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return port;
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}
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static bool
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intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
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{
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return i915_mmio_reg_valid(intel_dig_port->hdmi.hdmi_reg);
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}
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static const struct ddi_buf_trans *
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skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
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{
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@ -401,28 +395,34 @@ skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
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* in either FDI or DP modes only, as HDMI connections will work with both
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* of those
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*/
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static void intel_prepare_ddi_buffers(struct drm_i915_private *dev_priv,
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enum port port, bool supports_hdmi)
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void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 iboost_bit = 0;
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int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
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size;
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int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
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int hdmi_level;
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enum port port;
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const struct ddi_buf_trans *ddi_translations_fdi;
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const struct ddi_buf_trans *ddi_translations_dp;
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const struct ddi_buf_trans *ddi_translations_edp;
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const struct ddi_buf_trans *ddi_translations_hdmi;
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const struct ddi_buf_trans *ddi_translations;
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port = intel_ddi_get_encoder_port(encoder);
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hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
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if (IS_BROXTON(dev_priv)) {
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if (!supports_hdmi)
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if (encoder->type != INTEL_OUTPUT_HDMI)
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return;
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/* Vswing programming for HDMI */
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bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
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INTEL_OUTPUT_HDMI);
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return;
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} else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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}
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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ddi_translations_fdi = NULL;
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ddi_translations_dp =
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skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
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@ -468,30 +468,18 @@ static void intel_prepare_ddi_buffers(struct drm_i915_private *dev_priv,
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hdmi_default_entry = 7;
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}
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switch (port) {
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case PORT_A:
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switch (encoder->type) {
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case INTEL_OUTPUT_EDP:
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ddi_translations = ddi_translations_edp;
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size = n_edp_entries;
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break;
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case PORT_B:
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case PORT_C:
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case INTEL_OUTPUT_DISPLAYPORT:
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case INTEL_OUTPUT_HDMI:
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ddi_translations = ddi_translations_dp;
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size = n_dp_entries;
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break;
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case PORT_D:
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if (intel_dp_is_edp(dev_priv->dev, PORT_D)) {
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ddi_translations = ddi_translations_edp;
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size = n_edp_entries;
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} else {
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ddi_translations = ddi_translations_dp;
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size = n_dp_entries;
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}
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break;
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case PORT_E:
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if (ddi_translations_fdi)
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ddi_translations = ddi_translations_fdi;
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else
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ddi_translations = ddi_translations_dp;
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case INTEL_OUTPUT_ANALOG:
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ddi_translations = ddi_translations_fdi;
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size = n_dp_entries;
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break;
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default:
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@ -505,7 +493,7 @@ static void intel_prepare_ddi_buffers(struct drm_i915_private *dev_priv,
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ddi_translations[i].trans2);
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}
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if (!supports_hdmi)
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if (encoder->type != INTEL_OUTPUT_HDMI)
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return;
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/* Choose a good default if VBT is badly populated */
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@ -520,37 +508,6 @@ static void intel_prepare_ddi_buffers(struct drm_i915_private *dev_priv,
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ddi_translations_hdmi[hdmi_level].trans2);
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}
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/* Program DDI buffers translations for DP. By default, program ports A-D in DP
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* mode and port E for FDI.
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*/
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void intel_prepare_ddi(struct drm_device *dev)
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{
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struct intel_encoder *intel_encoder;
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bool visited[I915_MAX_PORTS] = { 0, };
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if (!HAS_DDI(dev))
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return;
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for_each_intel_encoder(dev, intel_encoder) {
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struct intel_digital_port *intel_dig_port;
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enum port port;
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bool supports_hdmi;
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if (intel_encoder->type == INTEL_OUTPUT_DSI)
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continue;
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ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
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if (visited[port])
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continue;
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supports_hdmi = intel_dig_port &&
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intel_dig_port_supports_hdmi(intel_dig_port);
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intel_prepare_ddi_buffers(to_i915(dev), port, supports_hdmi);
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visited[port] = true;
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}
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}
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static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
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enum port port)
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{
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@ -579,8 +536,14 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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u32 temp, i, rx_ctl_val;
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for_each_encoder_on_crtc(dev, crtc, encoder) {
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WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
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intel_prepare_ddi_buffer(encoder);
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}
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/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
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* mode set "sequence for CRT port" document:
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* - TP1 to TP2 time with the default value
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@ -2306,12 +2269,12 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
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static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
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{
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_private *dev_priv = to_i915(encoder->dev);
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struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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int type = intel_encoder->type;
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int hdmi_level;
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intel_prepare_ddi_buffer(intel_encoder);
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if (type == INTEL_OUTPUT_EDP) {
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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@ -2329,17 +2292,11 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
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intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
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intel_dp_start_link_train(intel_dp);
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if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
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if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
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intel_dp_stop_link_train(intel_dp);
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} else if (type == INTEL_OUTPUT_HDMI) {
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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if (IS_BROXTON(dev)) {
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hdmi_level = dev_priv->vbt.
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ddi_port_info[port].hdmi_level_shift;
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bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
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INTEL_OUTPUT_HDMI);
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}
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intel_hdmi->set_infoframes(encoder,
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crtc->config->has_hdmi_sink,
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&crtc->config->base.adjusted_mode);
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@ -9710,8 +9710,6 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
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val |= PCH_LP_PARTITION_LEVEL_DISABLE;
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I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
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}
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intel_prepare_ddi(dev);
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}
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static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
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@ -15312,7 +15310,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
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dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
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intel_prepare_ddi(dev);
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intel_init_clock_gating(dev);
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intel_enable_gt_powersave(dev);
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}
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@ -184,6 +184,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
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intel_mst->port = found->port;
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if (intel_dp->active_mst_links == 0) {
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intel_prepare_ddi_buffer(&intel_dig_port->base);
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intel_ddi_clk_select(&intel_dig_port->base, intel_crtc->config);
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intel_dp_set_link_params(intel_dp, intel_crtc->config);
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@ -1025,7 +1025,7 @@ void intel_crt_init(struct drm_device *dev);
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/* intel_ddi.c */
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void intel_ddi_clk_select(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config);
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void intel_prepare_ddi(struct drm_device *dev);
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void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
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void hsw_fdi_link_train(struct drm_crtc *crtc);
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void intel_ddi_init(struct drm_device *dev, enum port port);
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enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
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@ -626,7 +626,6 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
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static void skl_set_power_well(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well, bool enable)
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{
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struct drm_device *dev = dev_priv->dev;
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uint32_t tmp, fuse_status;
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uint32_t req_mask, state_mask;
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bool is_enabled, enable_requested, check_fuse_status = false;
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@ -670,17 +669,6 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
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!I915_READ(HSW_PWR_WELL_BIOS),
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"Invalid for power well status to be enabled, unless done by the BIOS, \
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when request is to disable!\n");
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if (power_well->data == SKL_DISP_PW_2) {
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/*
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* DDI buffer programming unnecessary during
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* driver-load/resume as it's already done
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* during modeset initialization then. It's
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* also invalid here as encoder list is still
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* uninitialized.
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*/
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if (!dev_priv->power_domains.initializing)
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intel_prepare_ddi(dev);
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}
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I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
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}
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