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drm/i915: Move i915_check_and_clear_faults to intel_reset.c
The code is logically about reset so it makes sense. It also enables making i915_clear_error_registers static. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190607115932.20271-1-tvrtko.ursulin@linux.intel.com
This commit is contained in:
parent
cf20b411bb
commit
6a8cc66ffe
4 changed files with 67 additions and 69 deletions
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@ -1166,8 +1166,8 @@ static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)
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GEN6_RING_FAULT_REG_POSTING_READ(engine);
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}
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void i915_clear_error_registers(struct drm_i915_private *i915,
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intel_engine_mask_t engine_mask)
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static void clear_error_registers(struct drm_i915_private *i915,
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intel_engine_mask_t engine_mask)
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{
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struct intel_uncore *uncore = &i915->uncore;
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u32 eir;
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@ -1205,6 +1205,69 @@ void i915_clear_error_registers(struct drm_i915_private *i915,
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}
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}
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static void gen6_check_faults(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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u32 fault;
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for_each_engine(engine, dev_priv, id) {
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fault = GEN6_RING_FAULT_REG_READ(engine);
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if (fault & RING_FAULT_VALID) {
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DRM_DEBUG_DRIVER("Unexpected fault\n"
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"\tAddr: 0x%08lx\n"
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"\tAddress space: %s\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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fault & PAGE_MASK,
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fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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}
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}
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}
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static void gen8_check_faults(struct drm_i915_private *dev_priv)
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{
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u32 fault = I915_READ(GEN8_RING_FAULT_REG);
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if (fault & RING_FAULT_VALID) {
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u32 fault_data0, fault_data1;
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u64 fault_addr;
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fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
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fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
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fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
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((u64)fault_data0 << 12);
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DRM_DEBUG_DRIVER("Unexpected fault\n"
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"\tAddr: 0x%08x_%08x\n"
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"\tAddress space: %s\n"
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"\tEngine ID: %d\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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upper_32_bits(fault_addr),
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lower_32_bits(fault_addr),
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fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
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GEN8_RING_FAULT_ENGINE_ID(fault),
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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}
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}
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void i915_check_and_clear_faults(struct drm_i915_private *i915)
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{
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/* From GEN8 onwards we only have one 'All Engine Fault Register' */
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if (INTEL_GEN(i915) >= 8)
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gen8_check_faults(i915);
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else if (INTEL_GEN(i915) >= 6)
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gen6_check_faults(i915);
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else
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return;
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clear_error_registers(i915, ALL_ENGINES);
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}
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/**
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* i915_handle_error - handle a gpu error
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* @i915: i915 device private
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@ -1253,7 +1316,7 @@ void i915_handle_error(struct drm_i915_private *i915,
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if (flags & I915_ERROR_CAPTURE) {
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i915_capture_error_state(i915, engine_mask, msg);
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i915_clear_error_registers(i915, engine_mask);
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clear_error_registers(i915, engine_mask);
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}
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/*
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@ -25,8 +25,7 @@ void i915_handle_error(struct drm_i915_private *i915,
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const char *fmt, ...);
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#define I915_ERROR_CAPTURE BIT(0)
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void i915_clear_error_registers(struct drm_i915_private *i915,
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intel_engine_mask_t engine_mask);
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void i915_check_and_clear_faults(struct drm_i915_private *i915);
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void i915_reset(struct drm_i915_private *i915,
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intel_engine_mask_t stalled_mask,
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@ -2300,69 +2300,6 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv)
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return IS_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active();
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}
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static void gen6_check_faults(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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u32 fault;
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for_each_engine(engine, dev_priv, id) {
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fault = GEN6_RING_FAULT_REG_READ(engine);
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if (fault & RING_FAULT_VALID) {
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DRM_DEBUG_DRIVER("Unexpected fault\n"
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"\tAddr: 0x%08lx\n"
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"\tAddress space: %s\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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fault & PAGE_MASK,
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fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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}
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}
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}
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static void gen8_check_faults(struct drm_i915_private *dev_priv)
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{
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u32 fault = I915_READ(GEN8_RING_FAULT_REG);
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if (fault & RING_FAULT_VALID) {
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u32 fault_data0, fault_data1;
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u64 fault_addr;
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fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
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fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
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fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
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((u64)fault_data0 << 12);
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DRM_DEBUG_DRIVER("Unexpected fault\n"
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"\tAddr: 0x%08x_%08x\n"
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"\tAddress space: %s\n"
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"\tEngine ID: %d\n"
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"\tSource ID: %d\n"
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"\tType: %d\n",
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upper_32_bits(fault_addr),
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lower_32_bits(fault_addr),
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fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
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GEN8_RING_FAULT_ENGINE_ID(fault),
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RING_FAULT_SRCID(fault),
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RING_FAULT_FAULT_TYPE(fault));
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}
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}
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void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
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{
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/* From GEN8 onwards we only have one 'All Engine Fault Register' */
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if (INTEL_GEN(dev_priv) >= 8)
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gen8_check_faults(dev_priv);
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else if (INTEL_GEN(dev_priv) >= 6)
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gen6_check_faults(dev_priv);
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else
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return;
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i915_clear_error_registers(dev_priv, ALL_ENGINES);
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}
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void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
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{
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struct i915_ggtt *ggtt = &dev_priv->ggtt;
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@ -646,7 +646,6 @@ int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
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void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
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void gen6_ppgtt_unpin_all(struct i915_hw_ppgtt *base);
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void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
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void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
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void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
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