mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-27 12:57:53 +00:00
- Drop pointless null checks and fix a scaler bug (Ville)
- Meteor Lake display fixes and clean-ups (RK, Jani, Andrzej, Mika, Imre) - Clean-up around flip done IRQ (Ville) - Fix eDP Meteor Lake bug (Jani) - Bigjoiner fixes (Ankit, Ville) - Cdclk/voltage_level cleanups and fixes (Ville) - DMC event stuff (Ville) - Remove dead code around intel_atomic_helper->free_list (Jouni) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEbSBwaO7dZQkcLOKj+mJfZA7rE8oFAmWAeT4ACgkQ+mJfZA7r E8qpvAf/eM8fA3qK0GCSQeh6ArvWwoZjZdtvfbIbUbVpEEbU2XsjDN/PiJF/dKVB Sae4qorosOh/+KruFj2vwzhQyOLSGlhic3kf/sDldgs2nhUiA+bcX8/fTOJ1yJ4U Hc3Z/rKoG5HoHAFD0AuPN0qY3QoRfxp6M7p3uVdR6NWEOTNzkaxxnbFD+UNnh8gy GcK/uzC+0NZRfsacvdqfKkb35Rx2pBnzx2dp+Fdl+bOWJgXZYVKWKlBijV4uIFf6 /7Q3689yeonKYj8WfmaboDGPXeUqP0CL8ojWkan4ey+HNHNJExn80oW05o9X6Hsl InbbVwVmoglojxBYTXoWESdYePL7Jg== =kINg -----END PGP SIGNATURE----- Merge tag 'drm-intel-next-2023-12-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next - Drop pointless null checks and fix a scaler bug (Ville) - Meteor Lake display fixes and clean-ups (RK, Jani, Andrzej, Mika, Imre) - Clean-up around flip done IRQ (Ville) - Fix eDP Meteor Lake bug (Jani) - Bigjoiner fixes (Ankit, Ville) - Cdclk/voltage_level cleanups and fixes (Ville) - DMC event stuff (Ville) - Remove dead code around intel_atomic_helper->free_list (Jouni) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZYB5XBRdWWgWoMKc@intel.com
This commit is contained in:
Dave Airlie
commit
6aaff21547
23 changed files with 305 additions and 281 deletions
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@ -608,7 +608,7 @@ static bool intel_crtc_active(struct intel_crtc *crtc)
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* crtc->state->active once we have proper CRTC states wired up
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* for atomic.
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*/
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return crtc && crtc->active && crtc->base.primary->state->fb &&
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return crtc->active && crtc->base.primary->state->fb &&
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crtc->config->hw.adjusted_mode.crtc_clock;
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}
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@ -3475,8 +3475,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
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if (!devdata->dsc)
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return false;
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if (crtc_state)
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fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);
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fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc);
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return true;
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}
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@ -1180,7 +1180,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
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/* force cdclk programming */
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dev_priv->display.cdclk.hw.cdclk = 0;
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/* force full PLL disable + enable */
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dev_priv->display.cdclk.hw.vco = -1;
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dev_priv->display.cdclk.hw.vco = ~0;
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}
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static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
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@ -1446,50 +1446,77 @@ static u8 bxt_calc_voltage_level(int cdclk)
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return DIV_ROUND_UP(cdclk, 25000);
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}
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static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
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const int voltage_level_max_cdclk[])
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{
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int voltage_level;
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for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
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if (cdclk <= voltage_level_max_cdclk[voltage_level])
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return voltage_level;
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}
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MISSING_CASE(cdclk);
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return num_voltage_levels - 1;
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}
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static u8 icl_calc_voltage_level(int cdclk)
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{
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if (cdclk > 556800)
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return 2;
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else if (cdclk > 312000)
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return 1;
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else
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return 0;
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static const int icl_voltage_level_max_cdclk[] = {
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[0] = 312000,
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[1] = 556800,
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[2] = 652800,
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};
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return calc_voltage_level(cdclk,
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ARRAY_SIZE(icl_voltage_level_max_cdclk),
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icl_voltage_level_max_cdclk);
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}
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static u8 ehl_calc_voltage_level(int cdclk)
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{
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if (cdclk > 326400)
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return 3;
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else if (cdclk > 312000)
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return 2;
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else if (cdclk > 180000)
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return 1;
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else
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return 0;
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static const int ehl_voltage_level_max_cdclk[] = {
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[0] = 180000,
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[1] = 312000,
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[2] = 326400,
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/*
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* Bspec lists the limit as 556.8 MHz, but some JSL
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* development boards (at least) boot with 652.8 MHz
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*/
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[3] = 652800,
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};
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return calc_voltage_level(cdclk,
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ARRAY_SIZE(ehl_voltage_level_max_cdclk),
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ehl_voltage_level_max_cdclk);
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}
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static u8 tgl_calc_voltage_level(int cdclk)
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{
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if (cdclk > 556800)
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return 3;
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else if (cdclk > 326400)
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return 2;
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else if (cdclk > 312000)
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return 1;
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else
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return 0;
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static const int tgl_voltage_level_max_cdclk[] = {
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[0] = 312000,
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[1] = 326400,
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[2] = 556800,
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[3] = 652800,
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};
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return calc_voltage_level(cdclk,
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ARRAY_SIZE(tgl_voltage_level_max_cdclk),
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tgl_voltage_level_max_cdclk);
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}
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static u8 rplu_calc_voltage_level(int cdclk)
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{
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if (cdclk > 556800)
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return 3;
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else if (cdclk > 480000)
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return 2;
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else if (cdclk > 312000)
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return 1;
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else
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return 0;
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static const int rplu_voltage_level_max_cdclk[] = {
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[0] = 312000,
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[1] = 480000,
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[2] = 556800,
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[3] = 652800,
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};
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return calc_voltage_level(cdclk,
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ARRAY_SIZE(rplu_voltage_level_max_cdclk),
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rplu_voltage_level_max_cdclk);
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}
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static void icl_readout_refclk(struct drm_i915_private *dev_priv,
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@ -1800,6 +1827,8 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
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return vco == ~0;
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}
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static const int cdclk_squash_len = 16;
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static int cdclk_squash_divider(u16 waveform)
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{
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return hweight16(waveform ?: 0xffff);
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@ -1811,7 +1840,6 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
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struct intel_cdclk_config *mid_cdclk_config)
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{
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u16 old_waveform, new_waveform, mid_waveform;
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int size = 16;
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int div = 2;
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/* Return if PLL is in an unknown state, force a complete disable and re-enable. */
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@ -1850,7 +1878,8 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
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}
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mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
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mid_cdclk_config->vco, size * div);
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mid_cdclk_config->vco,
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cdclk_squash_len * div);
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/* make sure the mid clock came out sane */
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@ -1878,9 +1907,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
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{
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int cdclk = cdclk_config->cdclk;
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int vco = cdclk_config->vco;
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u32 val;
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int unsquashed_cdclk;
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u16 waveform;
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int clock;
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u32 val;
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if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
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!cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
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@ -1897,15 +1926,13 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
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waveform = cdclk_squash_waveform(dev_priv, cdclk);
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if (waveform)
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clock = vco / 2;
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else
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clock = cdclk;
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unsquashed_cdclk = DIV_ROUND_CLOSEST(cdclk * cdclk_squash_len,
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cdclk_squash_divider(waveform));
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if (HAS_CDCLK_SQUASH(dev_priv))
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dg2_cdclk_squash_program(dev_priv, waveform);
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val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
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val = bxt_cdclk_cd2x_div_sel(dev_priv, unsquashed_cdclk, vco) |
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bxt_cdclk_cd2x_pipe(dev_priv, pipe);
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/*
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@ -2075,7 +2102,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
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dev_priv->display.cdclk.hw.cdclk = 0;
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/* force full PLL disable + enable */
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dev_priv->display.cdclk.hw.vco = -1;
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dev_priv->display.cdclk.hw.vco = ~0;
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}
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static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
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@ -3489,7 +3516,7 @@ static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
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.get_cdclk = bxt_get_cdclk,
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.set_cdclk = bxt_set_cdclk,
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.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
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.calc_voltage_level = tgl_calc_voltage_level,
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.calc_voltage_level = rplu_calc_voltage_level,
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};
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static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
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@ -553,8 +553,15 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
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intel_psr_lock(new_crtc_state);
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if (new_crtc_state->do_async_flip)
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if (new_crtc_state->do_async_flip) {
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spin_lock_irq(&crtc->base.dev->event_lock);
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/* arm the event for the flip done irq handler */
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crtc->flip_done_event = new_crtc_state->uapi.event;
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spin_unlock_irq(&crtc->base.dev->event_lock);
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new_crtc_state->uapi.event = NULL;
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return;
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}
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if (intel_crtc_needs_vblank_work(new_crtc_state))
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intel_crtc_vblank_work_init(new_crtc_state);
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@ -745,7 +745,6 @@ static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
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/* C20 basic DP 1.4 tables */
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static const struct intel_c20pll_state mtl_c20_dp_rbr = {
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.link_bit_rate = 162000,
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.clock = 162000,
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.tx = { 0xbe88, /* tx cfg0 */
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0x5800, /* tx cfg1 */
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@ -771,7 +770,6 @@ static const struct intel_c20pll_state mtl_c20_dp_rbr = {
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};
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static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
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.link_bit_rate = 270000,
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.clock = 270000,
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.tx = { 0xbe88, /* tx cfg0 */
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0x4800, /* tx cfg1 */
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@ -797,7 +795,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
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};
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static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
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.link_bit_rate = 540000,
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.clock = 540000,
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.tx = { 0xbe88, /* tx cfg0 */
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0x4800, /* tx cfg1 */
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@ -823,7 +820,6 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
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};
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static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
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.link_bit_rate = 810000,
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.clock = 810000,
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.tx = { 0xbe88, /* tx cfg0 */
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0x4800, /* tx cfg1 */
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@ -850,8 +846,7 @@ static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
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/* C20 basic DP 2.0 tables */
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static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
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.link_bit_rate = 1000000, /* 10 Gbps */
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.clock = 312500,
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.clock = 1000000, /* 10 Gbps */
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.tx = { 0xbe21, /* tx cfg0 */
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0x4800, /* tx cfg1 */
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0x0000, /* tx cfg2 */
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@ -875,8 +870,7 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
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};
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static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
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.link_bit_rate = 1350000, /* 13.5 Gbps */
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.clock = 421875,
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.clock = 1350000, /* 13.5 Gbps */
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.tx = { 0xbea0, /* tx cfg0 */
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0x4800, /* tx cfg1 */
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0x0000, /* tx cfg2 */
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@ -901,8 +895,7 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
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};
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static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
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.link_bit_rate = 2000000, /* 20 Gbps */
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.clock = 625000,
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.clock = 2000000, /* 20 Gbps */
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.tx = { 0xbe20, /* tx cfg0 */
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0x4800, /* tx cfg1 */
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0x0000, /* tx cfg2 */
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@ -1521,7 +1514,6 @@ static const struct intel_c10pll_state * const mtl_c10_hdmi_tables[] = {
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};
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static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
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.link_bit_rate = 25175,
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.clock = 25175,
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.tx = { 0xbe88, /* tx cfg0 */
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0x9800, /* tx cfg1 */
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@ -1547,7 +1539,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_25_175 = {
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};
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static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
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.link_bit_rate = 27000,
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.clock = 27000,
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.tx = { 0xbe88, /* tx cfg0 */
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0x9800, /* tx cfg1 */
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@ -1573,7 +1564,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_27_0 = {
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};
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static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
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.link_bit_rate = 74250,
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.clock = 74250,
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.tx = { 0xbe88, /* tx cfg0 */
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0x9800, /* tx cfg1 */
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@ -1599,7 +1589,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_74_25 = {
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};
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static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
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.link_bit_rate = 148500,
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.clock = 148500,
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.tx = { 0xbe88, /* tx cfg0 */
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0x9800, /* tx cfg1 */
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@ -1625,7 +1614,6 @@ static const struct intel_c20pll_state mtl_c20_hdmi_148_5 = {
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};
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static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
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.link_bit_rate = 594000,
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.clock = 594000,
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.tx = { 0xbe88, /* tx cfg0 */
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0x9800, /* tx cfg1 */
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@ -1651,8 +1639,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 = {
|
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};
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static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
|
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.link_bit_rate = 3000000,
|
||||
.clock = 166670,
|
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.clock = 3000000,
|
||||
.tx = { 0xbe98, /* tx cfg0 */
|
||||
0x9800, /* tx cfg1 */
|
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0x0000, /* tx cfg2 */
|
||||
|
|
@ -1677,8 +1664,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
|
|||
};
|
||||
|
||||
static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
|
||||
.link_bit_rate = 6000000,
|
||||
.clock = 333330,
|
||||
.clock = 6000000,
|
||||
.tx = { 0xbe98, /* tx cfg0 */
|
||||
0x9800, /* tx cfg1 */
|
||||
0x0000, /* tx cfg2 */
|
||||
|
|
@ -1703,8 +1689,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
|
|||
};
|
||||
|
||||
static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
|
||||
.link_bit_rate = 8000000,
|
||||
.clock = 444440,
|
||||
.clock = 8000000,
|
||||
.tx = { 0xbe98, /* tx cfg0 */
|
||||
0x9800, /* tx cfg1 */
|
||||
0x0000, /* tx cfg2 */
|
||||
|
|
@ -1729,8 +1714,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
|
|||
};
|
||||
|
||||
static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
|
||||
.link_bit_rate = 10000000,
|
||||
.clock = 555560,
|
||||
.clock = 10000000,
|
||||
.tx = { 0xbe98, /* tx cfg0 */
|
||||
0x9800, /* tx cfg1 */
|
||||
0x0000, /* tx cfg2 */
|
||||
|
|
@ -1755,8 +1739,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
|
|||
};
|
||||
|
||||
static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
|
||||
.link_bit_rate = 12000000,
|
||||
.clock = 666670,
|
||||
.clock = 12000000,
|
||||
.tx = { 0xbe98, /* tx cfg0 */
|
||||
0x9800, /* tx cfg1 */
|
||||
0x0000, /* tx cfg2 */
|
||||
|
|
@ -2005,7 +1988,6 @@ static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_
|
|||
else
|
||||
mpllb_ana_freq_vco = MPLLB_ANA_FREQ_VCO_0;
|
||||
|
||||
pll_state->link_bit_rate = pixel_clock;
|
||||
pll_state->clock = pixel_clock;
|
||||
pll_state->tx[0] = 0xbe88;
|
||||
pll_state->tx[1] = 0x9800;
|
||||
|
|
@ -2042,7 +2024,7 @@ static int intel_c20_phy_check_hdmi_link_rate(int clock)
|
|||
int i;
|
||||
|
||||
for (i = 0; tables[i]; i++) {
|
||||
if (clock == tables[i]->link_bit_rate)
|
||||
if (clock == tables[i]->clock)
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
|
|
@ -2094,7 +2076,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
|
|||
return -EINVAL;
|
||||
|
||||
for (i = 0; tables[i]; i++) {
|
||||
if (crtc_state->port_clock == tables[i]->link_bit_rate) {
|
||||
if (crtc_state->port_clock == tables[i]->clock) {
|
||||
crtc_state->cx0pll_state.c20 = *tables[i];
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -2117,7 +2099,7 @@ int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
|
|||
static bool intel_c20_use_mplla(u32 clock)
|
||||
{
|
||||
/* 10G and 20G rates use MPLLA */
|
||||
if (clock == 312500 || clock == 625000)
|
||||
if (clock == 1000000 || clock == 2000000)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
|
|
@ -2220,11 +2202,11 @@ static u8 intel_c20_get_dp_rate(u32 clock)
|
|||
return 6;
|
||||
case 432000: /* 4.32 Gbps eDP */
|
||||
return 7;
|
||||
case 312500: /* 10 Gbps DP2.0 */
|
||||
case 1000000: /* 10 Gbps DP2.0 */
|
||||
return 8;
|
||||
case 421875: /* 13.5 Gbps DP2.0 */
|
||||
case 1350000: /* 13.5 Gbps DP2.0 */
|
||||
return 9;
|
||||
case 625000: /* 20 Gbps DP2.0*/
|
||||
case 2000000: /* 20 Gbps DP2.0 */
|
||||
return 10;
|
||||
case 648000: /* 6.48 Gbps eDP*/
|
||||
return 11;
|
||||
|
|
@ -2242,13 +2224,13 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)
|
|||
return 0;
|
||||
|
||||
switch (clock) {
|
||||
case 166670: /* 3 Gbps */
|
||||
case 333330: /* 6 Gbps */
|
||||
case 666670: /* 12 Gbps */
|
||||
case 300000: /* 3 Gbps */
|
||||
case 600000: /* 6 Gbps */
|
||||
case 1200000: /* 12 Gbps */
|
||||
return 1;
|
||||
case 444440: /* 8 Gbps */
|
||||
case 800000: /* 8 Gbps */
|
||||
return 2;
|
||||
case 555560: /* 10 Gbps */
|
||||
case 1000000: /* 10 Gbps */
|
||||
return 3;
|
||||
default:
|
||||
MISSING_CASE(clock);
|
||||
|
|
@ -2259,7 +2241,7 @@ static u8 intel_c20_get_hdmi_rate(u32 clock)
|
|||
static bool is_dp2(u32 clock)
|
||||
{
|
||||
/* DP2.0 clock rates */
|
||||
if (clock == 312500 || clock == 421875 || clock == 625000)
|
||||
if (clock == 1000000 || clock == 1350000 || clock == 2000000)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
|
|
@ -2268,11 +2250,11 @@ static bool is_dp2(u32 clock)
|
|||
static bool is_hdmi_frl(u32 clock)
|
||||
{
|
||||
switch (clock) {
|
||||
case 166670: /* 3 Gbps */
|
||||
case 333330: /* 6 Gbps */
|
||||
case 444440: /* 8 Gbps */
|
||||
case 555560: /* 10 Gbps */
|
||||
case 666670: /* 12 Gbps */
|
||||
case 300000: /* 3 Gbps */
|
||||
case 600000: /* 6 Gbps */
|
||||
case 800000: /* 8 Gbps */
|
||||
case 1000000: /* 10 Gbps */
|
||||
case 1200000: /* 12 Gbps */
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
|
|
@ -2305,6 +2287,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
|
|||
const struct intel_c20pll_state *pll_state = &crtc_state->cx0pll_state.c20;
|
||||
bool dp = false;
|
||||
int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
|
||||
u32 clock = crtc_state->port_clock;
|
||||
bool cntx;
|
||||
int i;
|
||||
|
||||
|
|
@ -2343,7 +2326,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
|
|||
}
|
||||
|
||||
/* 3.3 mpllb or mplla configuration */
|
||||
if (intel_c20_use_mplla(pll_state->clock)) {
|
||||
if (intel_c20_use_mplla(clock)) {
|
||||
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
|
||||
if (cntx)
|
||||
intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,
|
||||
|
|
@ -2370,23 +2353,23 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
|
|||
/* 4. Program custom width to match the link protocol */
|
||||
intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_WIDTH,
|
||||
PHY_C20_CUSTOM_WIDTH_MASK,
|
||||
PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(pll_state->clock, dp)),
|
||||
PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)),
|
||||
MB_WRITE_COMMITTED);
|
||||
|
||||
/* 5. For DP or 6. For HDMI */
|
||||
if (dp) {
|
||||
intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
|
||||
BIT(6) | PHY_C20_CUSTOM_SERDES_MASK,
|
||||
BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(pll_state->clock)),
|
||||
BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)),
|
||||
MB_WRITE_COMMITTED);
|
||||
} else {
|
||||
intel_cx0_rmw(i915, encoder->port, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE,
|
||||
BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
|
||||
is_hdmi_frl(pll_state->clock) ? BIT(7) : 0,
|
||||
is_hdmi_frl(clock) ? BIT(7) : 0,
|
||||
MB_WRITE_COMMITTED);
|
||||
|
||||
intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
|
||||
intel_c20_get_hdmi_rate(pll_state->clock),
|
||||
intel_c20_get_hdmi_rate(clock),
|
||||
MB_WRITE_COMMITTED);
|
||||
}
|
||||
|
||||
|
|
@ -2485,7 +2468,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
|
|||
|
||||
val |= XELPDP_FORWARD_CLOCK_UNGATE;
|
||||
|
||||
if (is_hdmi_frl(crtc_state->port_clock))
|
||||
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
|
||||
is_hdmi_frl(crtc_state->port_clock))
|
||||
val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
|
||||
else
|
||||
val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
|
||||
|
|
|
|||
|
|
@ -3672,16 +3672,42 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
|
|||
AUDIO_OUTPUT_ENABLE(cpu_transcoder);
|
||||
}
|
||||
|
||||
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
|
||||
struct intel_crtc_state *crtc_state)
|
||||
static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
|
||||
crtc_state->min_voltage_level = 2;
|
||||
else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
|
||||
crtc_state->port_clock > 594000)
|
||||
crtc_state->min_voltage_level = 3;
|
||||
else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
|
||||
crtc_state->min_voltage_level = 1;
|
||||
if (crtc_state->port_clock > 594000)
|
||||
return 2;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
if (crtc_state->port_clock > 594000)
|
||||
return 3;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
if (crtc_state->port_clock > 594000)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 14)
|
||||
crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
|
||||
else if (DISPLAY_VER(dev_priv) >= 12)
|
||||
crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);
|
||||
else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
|
||||
crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);
|
||||
else if (DISPLAY_VER(dev_priv) >= 11)
|
||||
crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
|
||||
}
|
||||
|
||||
static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
|
||||
|
|
@ -3895,7 +3921,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
|
|||
pipe_config->lane_lat_optim_mask =
|
||||
bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
|
||||
|
||||
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
|
||||
intel_ddi_compute_min_voltage_level(pipe_config);
|
||||
|
||||
intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
|
||||
|
||||
|
|
@ -4175,7 +4201,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder,
|
|||
pipe_config->lane_lat_optim_mask =
|
||||
bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
|
||||
|
||||
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
|
||||
intel_ddi_compute_min_voltage_level(pipe_config);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -70,8 +70,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
|
|||
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
|
||||
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
|
||||
bool state);
|
||||
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
|
||||
struct intel_crtc_state *crtc_state);
|
||||
void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state);
|
||||
int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
|
||||
enum transcoder cpu_transcoder,
|
||||
bool enable, u32 hdcp_mask);
|
||||
|
|
|
|||
|
|
@ -3746,8 +3746,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
|
|||
if (!active)
|
||||
goto out;
|
||||
|
||||
intel_dsc_get_config(pipe_config);
|
||||
intel_bigjoiner_get_config(pipe_config);
|
||||
intel_dsc_get_config(pipe_config);
|
||||
|
||||
if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
|
||||
DISPLAY_VER(dev_priv) >= 11)
|
||||
|
|
@ -5926,6 +5926,17 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* FIXME: Bigjoiner+async flip is busted currently.
|
||||
* Remove this check once the issues are fixed.
|
||||
*/
|
||||
if (new_crtc_state->bigjoiner_pipes) {
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"[CRTC:%d:%s] async flip disallowed with bigjoiner\n",
|
||||
crtc->base.base.id, crtc->base.name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
|
||||
new_plane_state, i) {
|
||||
if (plane->pipe != crtc->pipe)
|
||||
|
|
@ -6963,24 +6974,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
|
|||
drm_WARN_ON(&dev_priv->drm, update_pipes);
|
||||
}
|
||||
|
||||
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_atomic_state *state, *next;
|
||||
struct llist_node *freed;
|
||||
|
||||
freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
|
||||
llist_for_each_entry_safe(state, next, freed, freed)
|
||||
drm_atomic_state_put(&state->base);
|
||||
}
|
||||
|
||||
void intel_atomic_helper_free_state_worker(struct work_struct *work)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
|
||||
|
||||
intel_atomic_helper_free_state(dev_priv);
|
||||
}
|
||||
|
||||
static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
|
||||
{
|
||||
struct drm_i915_private *i915 = to_i915(intel_state->base.dev);
|
||||
|
|
@ -7016,8 +7009,6 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
|
|||
drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
|
||||
drm_atomic_helper_commit_cleanup_done(&state->base);
|
||||
drm_atomic_state_put(&state->base);
|
||||
|
||||
intel_atomic_helper_free_state(i915);
|
||||
}
|
||||
|
||||
static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
|
||||
|
|
|
|||
|
|
@ -298,12 +298,6 @@ struct intel_display {
|
|||
const struct intel_audio_funcs *audio;
|
||||
} funcs;
|
||||
|
||||
/* Grouping using anonymous structs. Keep sorted. */
|
||||
struct intel_atomic_helper {
|
||||
struct llist_head free_list;
|
||||
struct work_struct free_work;
|
||||
} atomic_helper;
|
||||
|
||||
struct {
|
||||
/* backlight registers and fields in struct intel_panel */
|
||||
struct mutex lock;
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ struct drm_printer;
|
|||
#define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
|
||||
#define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl)
|
||||
#define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash)
|
||||
#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
|
||||
#define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13))
|
||||
#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
|
||||
#define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi)
|
||||
#define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
|
||||
|
|
|
|||
|
|
@ -259,10 +259,6 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
|
|||
if (ret)
|
||||
goto cleanup_vga_client_pw_domain_dmc;
|
||||
|
||||
init_llist_head(&i915->display.atomic_helper.free_list);
|
||||
INIT_WORK(&i915->display.atomic_helper.free_work,
|
||||
intel_atomic_helper_free_state_worker);
|
||||
|
||||
intel_init_quirks(i915);
|
||||
|
||||
intel_fbc_init(i915);
|
||||
|
|
@ -430,9 +426,6 @@ void intel_display_driver_remove(struct drm_i915_private *i915)
|
|||
flush_workqueue(i915->display.wq.flip);
|
||||
flush_workqueue(i915->display.wq.modeset);
|
||||
|
||||
flush_work(&i915->display.atomic_helper.free_work);
|
||||
drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list));
|
||||
|
||||
/*
|
||||
* MST topology needs to be suspended so we don't have any calls to
|
||||
* fbdev after it's finalized. MST will be destroyed later as part of
|
||||
|
|
|
|||
|
|
@ -340,18 +340,15 @@ static void flip_done_handler(struct drm_i915_private *i915,
|
|||
enum pipe pipe)
|
||||
{
|
||||
struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);
|
||||
struct drm_crtc_state *crtc_state = crtc->base.state;
|
||||
struct drm_pending_vblank_event *e = crtc_state->event;
|
||||
struct drm_device *dev = &i915->drm;
|
||||
unsigned long irqflags;
|
||||
|
||||
spin_lock_irqsave(&dev->event_lock, irqflags);
|
||||
spin_lock(&i915->drm.event_lock);
|
||||
|
||||
crtc_state->event = NULL;
|
||||
if (crtc->flip_done_event) {
|
||||
drm_crtc_send_vblank_event(&crtc->base, crtc->flip_done_event);
|
||||
crtc->flip_done_event = NULL;
|
||||
}
|
||||
|
||||
drm_crtc_send_vblank_event(&crtc->base, e);
|
||||
|
||||
spin_unlock_irqrestore(&dev->event_lock, irqflags);
|
||||
spin_unlock(&i915->drm.event_lock);
|
||||
}
|
||||
|
||||
static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
|
||||
|
|
|
|||
|
|
@ -684,8 +684,6 @@ struct intel_atomic_state {
|
|||
bool skip_intermediate_wm;
|
||||
|
||||
bool rps_interactive;
|
||||
|
||||
struct llist_node freed;
|
||||
};
|
||||
|
||||
struct intel_plane_state {
|
||||
|
|
@ -1022,7 +1020,6 @@ struct intel_c10pll_state {
|
|||
};
|
||||
|
||||
struct intel_c20pll_state {
|
||||
u32 link_bit_rate;
|
||||
u32 clock; /* in kHz */
|
||||
u16 tx[3];
|
||||
u16 cmn[4];
|
||||
|
|
@ -1476,6 +1473,9 @@ struct intel_crtc {
|
|||
|
||||
struct intel_crtc_state *config;
|
||||
|
||||
/* armed event for async flip */
|
||||
struct drm_pending_vblank_event *flip_done_event;
|
||||
|
||||
/* Access to these should be protected by dev_priv->irq_lock. */
|
||||
bool cpu_fifo_underrun_disabled;
|
||||
bool pch_fifo_underrun_disabled;
|
||||
|
|
|
|||
|
|
@ -335,77 +335,6 @@ static void disable_event_handler(struct drm_i915_private *i915,
|
|||
intel_de_write(i915, htp_reg, 0);
|
||||
}
|
||||
|
||||
static void
|
||||
disable_flip_queue_event(struct drm_i915_private *i915,
|
||||
i915_reg_t ctl_reg, i915_reg_t htp_reg)
|
||||
{
|
||||
u32 event_ctl;
|
||||
u32 event_htp;
|
||||
|
||||
event_ctl = intel_de_read(i915, ctl_reg);
|
||||
event_htp = intel_de_read(i915, htp_reg);
|
||||
if (event_ctl != (DMC_EVT_CTL_ENABLE |
|
||||
DMC_EVT_CTL_RECURRING |
|
||||
REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
|
||||
DMC_EVT_CTL_TYPE_EDGE_0_1) |
|
||||
REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
|
||||
DMC_EVT_CTL_EVENT_ID_CLK_MSEC)) ||
|
||||
!event_htp) {
|
||||
drm_dbg_kms(&i915->drm,
|
||||
"Unexpected DMC event configuration (control %08x htp %08x)\n",
|
||||
event_ctl, event_htp);
|
||||
return;
|
||||
}
|
||||
|
||||
disable_event_handler(i915, ctl_reg, htp_reg);
|
||||
}
|
||||
|
||||
static bool
|
||||
get_flip_queue_event_regs(struct drm_i915_private *i915, enum intel_dmc_id dmc_id,
|
||||
i915_reg_t *ctl_reg, i915_reg_t *htp_reg)
|
||||
{
|
||||
if (dmc_id == DMC_FW_MAIN) {
|
||||
if (DISPLAY_VER(i915) == 12) {
|
||||
*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 3);
|
||||
*htp_reg = DMC_EVT_HTP(i915, dmc_id, 3);
|
||||
|
||||
return true;
|
||||
}
|
||||
} else if (dmc_id >= DMC_FW_PIPEA && dmc_id <= DMC_FW_PIPED) {
|
||||
if (IS_DG2(i915)) {
|
||||
*ctl_reg = DMC_EVT_CTL(i915, dmc_id, 2);
|
||||
*htp_reg = DMC_EVT_HTP(i915, dmc_id, 2);
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static void
|
||||
disable_all_flip_queue_events(struct drm_i915_private *i915)
|
||||
{
|
||||
enum intel_dmc_id dmc_id;
|
||||
|
||||
/* TODO: check if the following applies to all D13+ platforms. */
|
||||
if (!IS_DG2(i915) && !IS_TIGERLAKE(i915))
|
||||
return;
|
||||
|
||||
for_each_dmc_id(dmc_id) {
|
||||
i915_reg_t ctl_reg;
|
||||
i915_reg_t htp_reg;
|
||||
|
||||
if (!has_dmc_id_fw(i915, dmc_id))
|
||||
continue;
|
||||
|
||||
if (!get_flip_queue_event_regs(i915, dmc_id, &ctl_reg, &htp_reg))
|
||||
continue;
|
||||
|
||||
disable_flip_queue_event(i915, ctl_reg, htp_reg);
|
||||
}
|
||||
}
|
||||
|
||||
static void disable_all_event_handlers(struct drm_i915_private *i915)
|
||||
{
|
||||
enum intel_dmc_id dmc_id;
|
||||
|
|
@ -493,6 +422,65 @@ void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
|
|||
intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
|
||||
}
|
||||
|
||||
static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915,
|
||||
enum intel_dmc_id dmc_id, i915_reg_t reg)
|
||||
{
|
||||
u32 offset = i915_mmio_reg_offset(reg);
|
||||
u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0));
|
||||
u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
|
||||
|
||||
return offset >= start && offset < end;
|
||||
}
|
||||
|
||||
static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915,
|
||||
enum intel_dmc_id dmc_id, i915_reg_t reg)
|
||||
{
|
||||
u32 offset = i915_mmio_reg_offset(reg);
|
||||
u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0));
|
||||
u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12));
|
||||
|
||||
return offset >= start && offset < end;
|
||||
}
|
||||
|
||||
static bool disable_dmc_evt(struct drm_i915_private *i915,
|
||||
enum intel_dmc_id dmc_id,
|
||||
i915_reg_t reg, u32 data)
|
||||
{
|
||||
if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg))
|
||||
return false;
|
||||
|
||||
/* keep all pipe DMC events disabled by default */
|
||||
if (dmc_id != DMC_FW_MAIN)
|
||||
return true;
|
||||
|
||||
/* also disable the flip queue event on the main DMC on TGL */
|
||||
if (IS_TIGERLAKE(i915) &&
|
||||
REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_CLK_MSEC)
|
||||
return true;
|
||||
|
||||
/* also disable the HRR event on the main DMC on TGL/ADLS */
|
||||
if ((IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915)) &&
|
||||
REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == DMC_EVT_CTL_EVENT_ID_VBLANK_A)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static u32 dmc_mmiodata(struct drm_i915_private *i915,
|
||||
struct intel_dmc *dmc,
|
||||
enum intel_dmc_id dmc_id, int i)
|
||||
{
|
||||
if (disable_dmc_evt(i915, dmc_id,
|
||||
dmc->dmc_info[dmc_id].mmioaddr[i],
|
||||
dmc->dmc_info[dmc_id].mmiodata[i]))
|
||||
return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
|
||||
DMC_EVT_CTL_TYPE_EDGE_0_1) |
|
||||
REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
|
||||
DMC_EVT_CTL_EVENT_ID_FALSE);
|
||||
else
|
||||
return dmc->dmc_info[dmc_id].mmiodata[i];
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_dmc_load_program() - write the firmware from memory to register.
|
||||
* @i915: i915 drm device.
|
||||
|
|
@ -532,7 +520,7 @@ void intel_dmc_load_program(struct drm_i915_private *i915)
|
|||
for_each_dmc_id(dmc_id) {
|
||||
for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) {
|
||||
intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i],
|
||||
dmc->dmc_info[dmc_id].mmiodata[i]);
|
||||
dmc_mmiodata(i915, dmc, dmc_id, i));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -540,13 +528,6 @@ void intel_dmc_load_program(struct drm_i915_private *i915)
|
|||
|
||||
gen9_set_dc_state_debugmask(i915);
|
||||
|
||||
/*
|
||||
* Flip queue events need to be disabled before enabling DC5/6.
|
||||
* i915 doesn't use the flip queue feature, so disable it already
|
||||
* here.
|
||||
*/
|
||||
disable_all_flip_queue_events(i915);
|
||||
|
||||
pipedmc_clock_gating_wa(i915, false);
|
||||
}
|
||||
|
||||
|
|
@ -742,9 +723,17 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
|
|||
return 0;
|
||||
}
|
||||
|
||||
drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id);
|
||||
for (i = 0; i < mmio_count; i++) {
|
||||
dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
|
||||
dmc_info->mmiodata[i] = mmiodata[i];
|
||||
|
||||
drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n",
|
||||
i, mmioaddr[i], mmiodata[i],
|
||||
is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" :
|
||||
is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "",
|
||||
disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i],
|
||||
dmc_info->mmiodata[i]) ? " (disabling)" : "");
|
||||
}
|
||||
dmc_info->mmio_count = mmio_count;
|
||||
dmc_info->start_mmioaddr = start_mmioaddr;
|
||||
|
|
|
|||
|
|
@ -60,6 +60,7 @@
|
|||
|
||||
#define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8)
|
||||
#define DMC_EVT_CTL_EVENT_ID_FALSE 0x01
|
||||
#define DMC_EVT_CTL_EVENT_ID_VBLANK_A 0x32 /* main DMC */
|
||||
/* An event handler scheduled to run at a 1 kHz frequency. */
|
||||
#define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf
|
||||
|
||||
|
|
|
|||
|
|
@ -650,19 +650,30 @@ intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
|
|||
const struct intel_crtc_state *crtc_state,
|
||||
u8 link_bw, u8 rate_select)
|
||||
{
|
||||
u8 link_config[2];
|
||||
u8 lane_count = crtc_state->lane_count;
|
||||
|
||||
/* Write the link configuration data */
|
||||
link_config[0] = link_bw;
|
||||
link_config[1] = crtc_state->lane_count;
|
||||
if (crtc_state->enhanced_framing)
|
||||
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
||||
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
|
||||
lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
||||
|
||||
/* eDP 1.4 rate select method. */
|
||||
if (!link_bw)
|
||||
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
|
||||
&rate_select, 1);
|
||||
if (link_bw) {
|
||||
/* DP and eDP v1.3 and earlier link bw set method. */
|
||||
u8 link_config[] = { link_bw, lane_count };
|
||||
|
||||
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
|
||||
ARRAY_SIZE(link_config));
|
||||
} else {
|
||||
/*
|
||||
* eDP v1.4 and later link rate set method.
|
||||
*
|
||||
* eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if
|
||||
* DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET.
|
||||
*
|
||||
* eDP v1.5 sinks allow choosing either, and the last choice
|
||||
* shall be active.
|
||||
*/
|
||||
drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
|
||||
drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -614,7 +614,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
|
|||
|
||||
intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
|
||||
|
||||
intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
|
||||
intel_ddi_compute_min_voltage_level(pipe_config);
|
||||
|
||||
intel_psr_compute_config(intel_dp, pipe_config, conn_state);
|
||||
|
||||
|
|
|
|||
|
|
@ -771,7 +771,7 @@ bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
|
|||
|
||||
bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
|
||||
{
|
||||
return fb && to_i915(fb->dev)->display.params.enable_dpt &&
|
||||
return to_i915(fb->dev)->display.params.enable_dpt &&
|
||||
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
|
||||
}
|
||||
|
||||
|
|
@ -1509,8 +1509,20 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p
|
|||
|
||||
size += remap_info->size;
|
||||
} else {
|
||||
unsigned int dst_stride = plane_view_dst_stride_tiles(fb, color_plane,
|
||||
remap_info->width);
|
||||
unsigned int dst_stride;
|
||||
|
||||
/*
|
||||
* The hardware automagically calculates the CCS AUX surface
|
||||
* stride from the main surface stride so can't really remap a
|
||||
* smaller subset (unless we'd remap in whole AUX page units).
|
||||
*/
|
||||
if (intel_fb_needs_pot_stride_remap(fb) &&
|
||||
intel_fb_is_ccs_modifier(fb->base.modifier))
|
||||
dst_stride = remap_info->src_stride;
|
||||
else
|
||||
dst_stride = remap_info->width;
|
||||
|
||||
dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride);
|
||||
|
||||
assign_chk_ovf(i915, remap_info->dst_stride, dst_stride);
|
||||
color_plane_info->mapping_stride = dst_stride *
|
||||
|
|
|
|||
|
|
@ -891,13 +891,13 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder cpu_trans
|
|||
return false;
|
||||
}
|
||||
|
||||
static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
|
||||
static u32 intel_get_frame_time_us(const struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
if (!cstate || !cstate->hw.active)
|
||||
if (!crtc_state->hw.active)
|
||||
return 0;
|
||||
|
||||
return DIV_ROUND_UP(1000 * 1000,
|
||||
drm_mode_vrefresh(&cstate->hw.adjusted_mode));
|
||||
drm_mode_vrefresh(&crtc_state->hw.adjusted_mode));
|
||||
}
|
||||
|
||||
static void psr2_program_idle_frames(struct intel_dp *intel_dp,
|
||||
|
|
|
|||
|
|
@ -1030,18 +1030,25 @@ static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enabl
|
|||
|
||||
__xelpdp_tc_phy_enable_tcss_power(tc, enable);
|
||||
|
||||
if ((!tc_phy_wait_for_ready(tc) ||
|
||||
!xelpdp_tc_phy_wait_for_tcss_power(tc, enable)) &&
|
||||
!drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY)) {
|
||||
if (enable) {
|
||||
__xelpdp_tc_phy_enable_tcss_power(tc, false);
|
||||
xelpdp_tc_phy_wait_for_tcss_power(tc, false);
|
||||
}
|
||||
if (enable && !tc_phy_wait_for_ready(tc))
|
||||
goto out_disable;
|
||||
|
||||
return false;
|
||||
}
|
||||
if (!xelpdp_tc_phy_wait_for_tcss_power(tc, enable))
|
||||
goto out_disable;
|
||||
|
||||
return true;
|
||||
|
||||
out_disable:
|
||||
if (drm_WARN_ON(&i915->drm, tc->mode == TC_PORT_LEGACY))
|
||||
return false;
|
||||
|
||||
if (!enable)
|
||||
return false;
|
||||
|
||||
__xelpdp_tc_phy_enable_tcss_power(tc, false);
|
||||
xelpdp_tc_phy_wait_for_tcss_power(tc, false);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
|
||||
|
|
|
|||
|
|
@ -1417,9 +1417,6 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv,
|
|||
static void set_color_conversion(struct drm_i915_private *dev_priv,
|
||||
const struct color_conversion *color_conversion)
|
||||
{
|
||||
if (!color_conversion)
|
||||
return;
|
||||
|
||||
intel_de_write(dev_priv, TV_CSC_Y,
|
||||
(color_conversion->ry << 16) | color_conversion->gy);
|
||||
intel_de_write(dev_priv, TV_CSC_Y2,
|
||||
|
|
@ -1454,9 +1451,6 @@ static void intel_tv_pre_enable(struct intel_atomic_state *state,
|
|||
int xpos, ypos;
|
||||
unsigned int xsize, ysize;
|
||||
|
||||
if (!tv_mode)
|
||||
return; /* can't happen (mode_prepare prevents this) */
|
||||
|
||||
tv_ctl = intel_de_read(dev_priv, TV_CTL);
|
||||
tv_ctl &= TV_CTL_SAVE;
|
||||
|
||||
|
|
|
|||
|
|
@ -812,13 +812,13 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
|
|||
}
|
||||
|
||||
static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
|
||||
bool *check_equal)
|
||||
bool *all_equal)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
|
||||
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
|
||||
i915_reg_t dsc_reg[2];
|
||||
int i, vdsc_per_pipe, dsc_reg_num;
|
||||
u32 val = 0;
|
||||
u32 val;
|
||||
|
||||
vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
|
||||
dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
|
||||
|
|
@ -827,20 +827,13 @@ static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
|
|||
|
||||
intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
|
||||
|
||||
if (check_equal)
|
||||
*check_equal = true;
|
||||
*all_equal = true;
|
||||
|
||||
for (i = 0; i < dsc_reg_num; i++) {
|
||||
u32 tmp;
|
||||
val = intel_de_read(i915, dsc_reg[0]);
|
||||
|
||||
tmp = intel_de_read(i915, dsc_reg[i]);
|
||||
|
||||
if (i == 0) {
|
||||
val = tmp;
|
||||
} else if (check_equal && tmp != val) {
|
||||
*check_equal = false;
|
||||
break;
|
||||
} else if (!check_equal) {
|
||||
for (i = 1; i < dsc_reg_num; i++) {
|
||||
if (intel_de_read(i915, dsc_reg[i]) != val) {
|
||||
*all_equal = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -504,7 +504,6 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
|
|||
{
|
||||
struct drm_plane *plane = NULL;
|
||||
struct intel_plane *intel_plane;
|
||||
struct intel_plane_state *plane_state = NULL;
|
||||
struct intel_crtc_scaler_state *scaler_state =
|
||||
&crtc_state->scaler_state;
|
||||
struct drm_atomic_state *drm_state = crtc_state->uapi.state;
|
||||
|
|
@ -536,6 +535,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
|
|||
|
||||
/* walkthrough scaler_users bits and start assigning scalers */
|
||||
for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
|
||||
struct intel_plane_state *plane_state = NULL;
|
||||
int *scaler_id;
|
||||
const char *name;
|
||||
int idx, ret;
|
||||
|
|
|
|||
Loading…
Reference in a new issue