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drm/amd/powerplay: implement sysfs for getting dpm clock
With the common interface print_clk_levels can get the following dpm clock: -pp_dpm_dcefclk -pp_dpm_fclk -pp_dpm_mclk -pp_dpm_sclk -pp_dpm_socclk Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2 changed files with 95 additions and 0 deletions
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@ -177,12 +177,82 @@ static int renoir_get_dpm_uclk_limited(struct smu_context *smu, uint32_t *clock,
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}
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static int renoir_print_clk_levels(struct smu_context *smu,
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enum smu_clk_type clk_type, char *buf)
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{
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int i, size = 0, ret = 0;
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uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
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DpmClocks_t *clk_table = smu->smu_table.clocks_table;
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SmuMetrics_t metrics = {0};
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if (!clk_table || clk_type >= SMU_CLK_COUNT)
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return -EINVAL;
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ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
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(void *)&metrics, false);
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if (ret)
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return ret;
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switch (clk_type) {
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case SMU_GFXCLK:
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case SMU_SCLK:
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/* retirve table returned paramters unit is MHz */
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cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
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ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, &min, &max);
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if (!ret) {
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/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
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if (cur_value == max)
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i = 2;
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else if (cur_value == min)
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i = 0;
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else
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i = 1;
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size += sprintf(buf + size, "0: %uMhz %s\n", min,
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i == 0 ? "*" : "");
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size += sprintf(buf + size, "1: %uMhz %s\n",
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i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
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i == 1 ? "*" : "");
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size += sprintf(buf + size, "2: %uMhz %s\n", max,
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i == 2 ? "*" : "");
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}
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return size;
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case SMU_SOCCLK:
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count = NUM_SOCCLK_DPM_LEVELS;
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cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
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break;
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case SMU_MCLK:
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count = NUM_MEMCLK_DPM_LEVELS;
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cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
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break;
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case SMU_DCEFCLK:
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count = NUM_DCFCLK_DPM_LEVELS;
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cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
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break;
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case SMU_FCLK:
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count = NUM_FCLK_DPM_LEVELS;
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cur_value = metrics.ClockFrequency[CLOCK_FCLK];
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < count; i++) {
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GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
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size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
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cur_value == value ? "*" : "");
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}
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return size;
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}
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static const struct pptable_funcs renoir_ppt_funcs = {
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.get_smu_msg_index = renoir_get_smu_msg_index,
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.get_smu_table_index = renoir_get_smu_table_index,
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.tables_init = renoir_tables_init,
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.set_power_state = NULL,
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.get_dpm_uclk_limited = renoir_get_dpm_uclk_limited,
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.print_clk_levels = renoir_print_clk_levels,
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};
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void renoir_set_ppt_funcs(struct smu_context *smu)
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@ -25,4 +25,29 @@
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extern void renoir_set_ppt_funcs(struct smu_context *smu);
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/* UMD PState Renoir Msg Parameters in MHz */
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#define RENOIR_UMD_PSTATE_GFXCLK 700
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#define RENOIR_UMD_PSTATE_SOCCLK 678
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#define RENOIR_UMD_PSTATE_FCLK 800
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#define GET_DPM_CUR_FREQ(table, clk_type, dpm_level, freq) \
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do { \
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switch (clk_type) { \
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case SMU_SOCCLK: \
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freq = table->SocClocks[dpm_level].Freq; \
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break; \
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case SMU_MCLK: \
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freq = table->MemClocks[dpm_level].Freq; \
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break; \
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case SMU_DCEFCLK: \
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freq = table->DcfClocks[dpm_level].Freq; \
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break; \
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case SMU_FCLK: \
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freq = table->FClocks[dpm_level].Freq; \
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break; \
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default: \
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break; \
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} \
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} while (0)
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#endif
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