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drm/exynos: mixer: Make plane alpha configurable
The mixer hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20180913 using modetest. Signed-off-by: Christoph Manszewski <c.manszewski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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parent
482582c021
commit
6ac99a328e
4 changed files with 30 additions and 16 deletions
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@ -93,6 +93,7 @@ struct exynos_drm_plane {
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#define EXYNOS_DRM_PLANE_CAP_ZPOS (1 << 2)
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#define EXYNOS_DRM_PLANE_CAP_TILE (1 << 3)
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#define EXYNOS_DRM_PLANE_CAP_PIX_BLEND (1 << 4)
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#define EXYNOS_DRM_PLANE_CAP_WIN_BLEND (1 << 5)
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/*
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* Exynos DRM plane configuration structure.
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@ -325,5 +325,8 @@ int exynos_plane_init(struct drm_device *dev,
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if (config->capabilities & EXYNOS_DRM_PLANE_CAP_PIX_BLEND)
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drm_plane_create_blend_mode_property(plane, supported_modes);
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if (config->capabilities & EXYNOS_DRM_PLANE_CAP_WIN_BLEND)
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drm_plane_create_alpha_property(plane);
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return 0;
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}
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@ -132,7 +132,8 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
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.num_pixel_formats = ARRAY_SIZE(mixer_formats),
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.capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
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EXYNOS_DRM_PLANE_CAP_ZPOS |
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EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
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EXYNOS_DRM_PLANE_CAP_PIX_BLEND |
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
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}, {
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.zpos = 1,
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.type = DRM_PLANE_TYPE_CURSOR,
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@ -140,7 +141,8 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
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.num_pixel_formats = ARRAY_SIZE(mixer_formats),
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.capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE |
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EXYNOS_DRM_PLANE_CAP_ZPOS |
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EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
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EXYNOS_DRM_PLANE_CAP_PIX_BLEND |
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
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}, {
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.zpos = 2,
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.type = DRM_PLANE_TYPE_OVERLAY,
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@ -148,7 +150,8 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = {
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.num_pixel_formats = ARRAY_SIZE(vp_formats),
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.capabilities = EXYNOS_DRM_PLANE_CAP_SCALE |
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EXYNOS_DRM_PLANE_CAP_ZPOS |
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EXYNOS_DRM_PLANE_CAP_TILE,
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EXYNOS_DRM_PLANE_CAP_TILE |
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
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},
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};
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@ -311,8 +314,9 @@ static void vp_default_filter(struct mixer_context *ctx)
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}
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static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
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unsigned int pixel_alpha)
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unsigned int pixel_alpha, unsigned int alpha)
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{
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u32 win_alpha = alpha >> 8;
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u32 val;
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val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
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@ -328,21 +332,24 @@ static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
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val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
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break;
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}
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if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
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val |= MXR_GRP_CFG_WIN_BLEND_EN;
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val |= win_alpha;
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}
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mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win),
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val, MXR_GRP_CFG_MISC_MASK);
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}
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static void mixer_cfg_vp_blend(struct mixer_context *ctx)
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static void mixer_cfg_vp_blend(struct mixer_context *ctx, unsigned int alpha)
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{
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u32 val;
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u32 win_alpha = alpha >> 8;
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u32 val = 0;
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/*
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* No blending at the moment since the NV12/NV21 pixelformats don't
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* have an alpha channel. However the mixer supports a global alpha
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* value for a layer. Once this functionality is exposed, we can
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* support blending of the video layer through this.
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*/
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val = 0;
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if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
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val |= MXR_VID_CFG_BLEND_EN;
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val |= win_alpha;
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}
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mixer_reg_write(ctx, MXR_VIDEO_CFG, val);
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}
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@ -538,7 +545,7 @@ static void vp_video_buffer(struct mixer_context *ctx,
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vp_reg_write(ctx, VP_BOT_C_PTR, chroma_addr[1]);
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mixer_cfg_layer(ctx, plane->index, priority, true);
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mixer_cfg_vp_blend(ctx);
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mixer_cfg_vp_blend(ctx, state->base.alpha);
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spin_unlock_irqrestore(&ctx->reg_slock, flags);
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@ -631,7 +638,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx,
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mixer_reg_write(ctx, MXR_GRAPHIC_BASE(win), dma_addr);
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mixer_cfg_layer(ctx, win, priority, true);
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mixer_cfg_gfx_blend(ctx, win, pixel_alpha);
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mixer_cfg_gfx_blend(ctx, win, pixel_alpha, state->base.alpha);
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/* layer update mandatory for mixer 16.0.33.0 */
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if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
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@ -109,12 +109,15 @@
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#define MXR_CFG_SCAN_HD (1 << 0)
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#define MXR_CFG_SCAN_MASK 0x47
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/* bits for MXR_VIDEO_CFG */
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#define MXR_VID_CFG_BLEND_EN (1 << 16)
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/* bits for MXR_GRAPHICn_CFG */
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#define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21)
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#define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20)
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#define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17)
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#define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16)
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#define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20))
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#define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20) | 0xff)
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#define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8)
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#define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0)
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#define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0)
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