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cpupower: mperf_monitor: Update cpupower to use the RDPRU instruction
AMD Zen 2 introduces the RDPRU instruction which can be used to access some processor registers which are typically only accessible in privilege level 0. ECX specifies the register to read and EDX:EAX will contain the value read. ECX: 0 - Register MPERF 1 - Register APERF This has the added advantage of not having to use the msr module, since the userspace to kernel transitions which occur during each read_msr() might cause APERF and MPERF to go out of sync. Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> Acked-by: Thomas Renninger <trenn@suse.de> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
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3 changed files with 25 additions and 0 deletions
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@ -131,6 +131,10 @@ int get_cpu_info(struct cpupower_cpu_info *cpu_info)
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if (ext_cpuid_level >= 0x80000007 &&
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(cpuid_edx(0x80000007) & (1 << 9)))
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cpu_info->caps |= CPUPOWER_CAP_AMD_CBP;
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if (ext_cpuid_level >= 0x80000008 &&
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cpuid_ebx(0x80000008) & (1 << 4))
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cpu_info->caps |= CPUPOWER_CAP_AMD_RDPRU;
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}
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if (cpu_info->vendor == X86_VENDOR_INTEL) {
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@ -69,6 +69,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
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#define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010
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#define CPUPOWER_CAP_IS_SNB 0x00000020
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#define CPUPOWER_CAP_INTEL_IDA 0x00000040
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#define CPUPOWER_CAP_AMD_RDPRU 0x00000080
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#define CPUPOWER_AMD_CPBDIS 0x02000000
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@ -19,6 +19,10 @@
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#define MSR_APERF 0xE8
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#define MSR_MPERF 0xE7
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#define RDPRU ".byte 0x0f, 0x01, 0xfd"
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#define RDPRU_ECX_MPERF 0
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#define RDPRU_ECX_APERF 1
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#define MSR_TSC 0x10
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#define MSR_AMD_HWCR 0xc0010015
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@ -89,6 +93,8 @@ static int mperf_get_tsc(unsigned long long *tsc)
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static int get_aperf_mperf(int cpu, unsigned long long *aval,
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unsigned long long *mval)
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{
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unsigned long low_a, high_a;
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unsigned long low_m, high_m;
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int ret;
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/*
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@ -101,6 +107,20 @@ static int get_aperf_mperf(int cpu, unsigned long long *aval,
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return 1;
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}
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if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_RDPRU) {
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asm volatile(RDPRU
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: "=a" (low_a), "=d" (high_a)
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: "c" (RDPRU_ECX_APERF));
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asm volatile(RDPRU
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: "=a" (low_m), "=d" (high_m)
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: "c" (RDPRU_ECX_MPERF));
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*aval = ((low_a) | (high_a) << 32);
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*mval = ((low_m) | (high_m) << 32);
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return 0;
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}
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ret = read_msr(cpu, MSR_APERF, aval);
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ret |= read_msr(cpu, MSR_MPERF, mval);
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