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[ARM] Feroceon: fix function alignment in proc-feroceon.S
One overzealous .align 10 fixed, and a few .align5 added. Signed-off-by: Nicolas Pitre <nico@marvell.com>
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commit
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1 changed files with 10 additions and 3 deletions
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@ -93,7 +93,7 @@ ENTRY(cpu_feroceon_reset)
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*
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* Called with IRQs disabled
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*/
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.align 10
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.align 5
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ENTRY(cpu_feroceon_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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@ -106,6 +106,7 @@ ENTRY(cpu_feroceon_do_idle)
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_all)
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/* FALLTHROUGH */
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@ -135,6 +136,7 @@ __flush_whole_cache:
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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@ -163,6 +165,7 @@ ENTRY(feroceon_flush_user_cache_range)
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_coherent_kern_range)
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/* FALLTHROUGH */
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@ -194,6 +197,7 @@ ENTRY(feroceon_coherent_user_range)
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*
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* - addr - page aligned address
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*/
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.align 5
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ENTRY(feroceon_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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@ -218,6 +222,7 @@ ENTRY(feroceon_flush_kern_dcache_page)
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*
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* (same as v4wb)
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*/
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.align 5
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ENTRY(feroceon_dma_inv_range)
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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@ -241,6 +246,7 @@ ENTRY(feroceon_dma_inv_range)
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*
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* (same as v4wb)
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*/
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.align 5
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ENTRY(feroceon_dma_clean_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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@ -258,10 +264,10 @@ ENTRY(feroceon_dma_clean_range)
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1:
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mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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@ -279,6 +285,7 @@ ENTRY(feroceon_cache_fns)
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.long feroceon_dma_clean_range
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.long feroceon_dma_flush_range
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.align 5
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ENTRY(cpu_feroceon_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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