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clk: imx: imx93: Add nic and A55 clk
The A55 clock logic as below: A55_PLL ----------------->\ A55_SEL-->A55_CORE A55_CCM_ROOT--->A55_GATE->/ Add A55 CPU clk to support freq change. Add NIC CLK to reflect the clk status Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
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5fd7b00ca2
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6b60c3ae3e
1 changed files with 15 additions and 2 deletions
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@ -33,6 +33,7 @@ static u32 share_count_sai2;
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static u32 share_count_sai3;
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static u32 share_count_mub;
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static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
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static const char *parent_names[MAX_SEL][4] = {
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{"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"},
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{"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"},
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@ -55,7 +56,7 @@ static const struct imx93_clk_root {
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/* a55/m33/bus critical clk for system run */
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{ IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
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{ IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
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{ IMX93_CLK_A55, "a55_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
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{ IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
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{ IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
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{ IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
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{ IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
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@ -117,6 +118,7 @@ static const struct imx93_clk_root {
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{ IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, },
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{ IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, },
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{ IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, },
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{ IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, },
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{ IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, },
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{ IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, },
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{ IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, },
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@ -153,7 +155,7 @@ static const struct imx93_clk_ccgr {
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unsigned long flags;
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u32 *shared_count;
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} ccgr_array[] = {
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{ IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, },
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{ IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, },
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/* M33 critical clk for system run */
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{ IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL },
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{ IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, },
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@ -291,6 +293,9 @@ static int imx93_clocks_probe(struct platform_device *pdev)
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if (WARN_ON(!anatop_base))
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return -ENOMEM;
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clks[IMX93_CLK_ARM_PLL] = imx_clk_fracn_gppll_integer("arm_pll", "osc_24m",
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anatop_base + 0x1000,
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&imx_fracn_gppll_integer);
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clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200,
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&imx_fracn_gppll);
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clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400,
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@ -318,6 +323,14 @@ static int imx93_clocks_probe(struct platform_device *pdev)
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ccgr->shared_count);
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}
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clks[IMX93_CLK_A55_SEL] = imx_clk_hw_mux2("a55_sel", base + 0x4820, 0, 1, a55_core_sels,
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ARRAY_SIZE(a55_core_sels));
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clks[IMX93_CLK_A55_CORE] = imx_clk_hw_cpu("a55_core", "a55_sel",
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clks[IMX93_CLK_A55_SEL]->clk,
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clks[IMX93_CLK_A55_SEL]->clk,
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clks[IMX93_CLK_ARM_PLL]->clk,
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clks[IMX93_CLK_A55_GATE]->clk);
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imx_check_clk_hws(clks, IMX93_CLK_END);
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
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