drm/amdgpu: fix mmhub register base coding error
commit347fafe0eb
upstream. fix MMHUB register base coding error. Fixes:ec6837591f
("drm/amdgpu/gmc10: program the smallK fragment size") Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -319,7 +319,7 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
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tmp = mmMMVM_L2_CNTL5_DEFAULT;
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
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WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
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}
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static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
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@ -243,7 +243,7 @@ static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
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tmp = mmMMVM_L2_CNTL5_DEFAULT;
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
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WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
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WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL5, tmp);
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}
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static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)
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@ -275,7 +275,7 @@ static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
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tmp = regMMVM_L2_CNTL5_DEFAULT;
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
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WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
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}
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static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev)
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@ -269,7 +269,7 @@ static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
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tmp = regMMVM_L2_CNTL5_DEFAULT;
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
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WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
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}
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static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
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@ -268,7 +268,7 @@ static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)
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tmp = regMMVM_L2_CNTL5_DEFAULT;
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tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
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WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
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WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp);
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}
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static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)
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