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arm64: ARM: Fix the Generic Timers interrupt active level description
The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional description" that generic timers provide an active-LOW interrupt output. Fix the device trees to correctly describe this. While doing this update the CPU mask to match the number of described CPUs as well. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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4190436096
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3 changed files with 12 additions and 12 deletions
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@ -78,10 +78,10 @@ gic: interrupt-controller@2c001000 {
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timer {
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timer {
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compatible = "arm,armv8-timer";
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff01>,
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interrupts = <1 13 0xf08>,
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<1 14 0xff01>,
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<1 14 0xf08>,
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<1 11 0xff01>,
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<1 11 0xf08>,
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<1 10 0xff01>;
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<1 10 0xf08>;
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clock-frequency = <100000000>;
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clock-frequency = <100000000>;
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};
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};
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@ -98,10 +98,10 @@ gic: interrupt-controller@2c001000 {
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timer {
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timer {
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compatible = "arm,armv8-timer";
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_EDGE_RISING)>;
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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pmu {
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pmu {
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@ -81,10 +81,10 @@ gic: interrupt-controller@2c001000 {
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timer {
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timer {
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compatible = "arm,armv8-timer";
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff01>,
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interrupts = <1 13 0xf08>,
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<1 14 0xff01>,
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<1 14 0xf08>,
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<1 11 0xff01>,
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<1 11 0xf08>,
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<1 10 0xff01>;
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<1 10 0xf08>;
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clock-frequency = <100000000>;
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clock-frequency = <100000000>;
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};
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};
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