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r8169: use spinlock to protect access to registers Config2 and Config5
For disabling ASPM during NAPI poll we'll have to access both registers in atomic context. Use a spinlock to protect access. Reviewed-by: Simon Horman <simon.horman@corigine.com> Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Tested-by: Holger Hoffstätte <holger@applied-asynchrony.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
91c8643578
commit
6bc6c4e689
1 changed files with 37 additions and 10 deletions
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@ -613,6 +613,7 @@ struct rtl8169_private {
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struct work_struct work;
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} wk;
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spinlock_t config25_lock;
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spinlock_t mac_ocp_lock;
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unsigned supports_gmii:1;
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@ -677,6 +678,28 @@ static void rtl_pci_commit(struct rtl8169_private *tp)
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RTL_R8(tp, ChipCmd);
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}
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static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
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{
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unsigned long flags;
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u8 val;
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spin_lock_irqsave(&tp->config25_lock, flags);
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val = RTL_R8(tp, Config2);
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RTL_W8(tp, Config2, (val & ~clear) | set);
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spin_unlock_irqrestore(&tp->config25_lock, flags);
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}
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static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
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{
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unsigned long flags;
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u8 val;
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spin_lock_irqsave(&tp->config25_lock, flags);
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val = RTL_R8(tp, Config5);
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RTL_W8(tp, Config5, (val & ~clear) | set);
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spin_unlock_irqrestore(&tp->config25_lock, flags);
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}
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static bool rtl_is_8125(struct rtl8169_private *tp)
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{
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return tp->mac_version >= RTL_GIGA_MAC_VER_61;
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@ -1363,6 +1386,7 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
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{ WAKE_MAGIC, Config3, MagicPacket }
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};
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unsigned int i, tmp = ARRAY_SIZE(cfg);
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unsigned long flags;
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u8 options;
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rtl_unlock_config_regs(tp);
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@ -1381,12 +1405,14 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
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r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
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}
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spin_lock_irqsave(&tp->config25_lock, flags);
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for (i = 0; i < tmp; i++) {
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options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
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if (wolopts & cfg[i].opt)
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options |= cfg[i].mask;
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RTL_W8(tp, cfg[i].reg, options);
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}
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spin_unlock_irqrestore(&tp->config25_lock, flags);
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
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@ -1398,10 +1424,10 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
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case RTL_GIGA_MAC_VER_34:
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case RTL_GIGA_MAC_VER_37:
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case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
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options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
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if (wolopts)
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options |= PME_SIGNAL;
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RTL_W8(tp, Config2, options);
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rtl_mod_config2(tp, 0, PME_SIGNAL);
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else
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rtl_mod_config2(tp, PME_SIGNAL, 0);
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break;
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default:
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break;
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@ -2704,8 +2730,8 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
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{
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/* Don't enable ASPM in the chip if OS can't control ASPM */
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if (enable && tp->aspm_manageable) {
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RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
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RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
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rtl_mod_config5(tp, 0, ASPM_en);
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rtl_mod_config2(tp, 0, ClkReqEn);
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switch (tp->mac_version) {
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case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
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@ -2728,8 +2754,8 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
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break;
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}
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RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
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RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
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rtl_mod_config2(tp, ClkReqEn, 0);
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rtl_mod_config5(tp, ASPM_en, 0);
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}
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udelay(10);
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@ -2890,7 +2916,7 @@ static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
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RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
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RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
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RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
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rtl_mod_config5(tp, Spi_en, 0);
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}
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static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
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@ -2923,7 +2949,7 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
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RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
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RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
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RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
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rtl_mod_config5(tp, Spi_en, 0);
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rtl_hw_aspm_clkreq_enable(tp, true);
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}
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@ -2946,7 +2972,7 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp)
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RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
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RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
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RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
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RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
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rtl_mod_config5(tp, Spi_en, 0);
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rtl8168_config_eee_mac(tp);
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}
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@ -5203,6 +5229,7 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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tp->eee_adv = -1;
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tp->ocp_base = OCP_STD_PHY_BASE;
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spin_lock_init(&tp->config25_lock);
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spin_lock_init(&tp->mac_ocp_lock);
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dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
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