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clk: renesas: r9a06g032: Switch to .determine_rate()
As the .round_rate() callback returns a long clock rate, it cannot return clock rates that do not fit in signed long, but do fit in unsigned long. Hence switch the divider clocks on RZ/N1 from the old .round_rate() callback to the newer .determine_rate() callback, which does not suffer from this limitation. Note that range checking is not yet implemented. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7a384d02b85cdaac4a0e2b357582c8244b9a6f98.1617282116.git.geert+renesas@glider.be
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02c69593e6
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1 changed files with 13 additions and 12 deletions
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@ -604,20 +604,19 @@ r9a06g032_div_clamp_div(struct r9a06g032_clk_div *clk,
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return div;
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}
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static long
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r9a06g032_div_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *prate)
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static int
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r9a06g032_div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
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{
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struct r9a06g032_clk_div *clk = to_r9a06g032_div(hw);
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u32 div = DIV_ROUND_UP(*prate, rate);
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u32 div = DIV_ROUND_UP(req->best_parent_rate, req->rate);
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pr_devel("%s %pC %ld (prate %ld) (wanted div %u)\n", __func__,
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hw->clk, rate, *prate, div);
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hw->clk, req->rate, req->best_parent_rate, div);
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pr_devel(" min %d (%ld) max %d (%ld)\n",
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clk->min, DIV_ROUND_UP(*prate, clk->min),
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clk->max, DIV_ROUND_UP(*prate, clk->max));
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clk->min, DIV_ROUND_UP(req->best_parent_rate, clk->min),
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clk->max, DIV_ROUND_UP(req->best_parent_rate, clk->max));
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div = r9a06g032_div_clamp_div(clk, rate, *prate);
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div = r9a06g032_div_clamp_div(clk, req->rate, req->best_parent_rate);
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/*
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* this is a hack. Currently the serial driver asks for a clock rate
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* that is 16 times the baud rate -- and that is wildly outside the
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@ -630,11 +629,13 @@ r9a06g032_div_round_rate(struct clk_hw *hw,
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if (clk->index == R9A06G032_DIV_UART ||
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clk->index == R9A06G032_DIV_P2_PG) {
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pr_devel("%s div uart hack!\n", __func__);
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return clk_get_rate(hw->clk);
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req->rate = clk_get_rate(hw->clk);
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return 0;
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}
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req->rate = DIV_ROUND_UP(req->best_parent_rate, div);
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pr_devel("%s %pC %ld / %u = %ld\n", __func__, hw->clk,
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*prate, div, DIV_ROUND_UP(*prate, div));
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return DIV_ROUND_UP(*prate, div);
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req->best_parent_rate, div, req->rate);
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return 0;
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}
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static int
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@ -663,7 +664,7 @@ r9a06g032_div_set_rate(struct clk_hw *hw,
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static const struct clk_ops r9a06g032_clk_div_ops = {
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.recalc_rate = r9a06g032_div_recalc_rate,
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.round_rate = r9a06g032_div_round_rate,
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.determine_rate = r9a06g032_div_determine_rate,
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.set_rate = r9a06g032_div_set_rate,
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};
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