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drm/amdgpu: Remove duplicate code in gfx_v8_0.c
There are no any logical changes here. 1. if kcq can be enabled via kiq, we don't need to do kiq ring test. 2. amdgpu_ring_test_ring function can be used to sync the ring complete, remove the duplicate code. v2: alloc 6 (not 7) dws for unmap_queues Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f1df06d0f9
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6c10b5cc4e
1 changed files with 13 additions and 67 deletions
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@ -4604,7 +4604,6 @@ static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
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static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
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uint32_t scratch, tmp = 0;
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uint64_t queue_mask = 0;
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int r, i;
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@ -4623,17 +4622,10 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
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queue_mask |= (1ull << i);
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}
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r = amdgpu_gfx_scratch_get(adev, &scratch);
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if (r) {
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DRM_ERROR("Failed to get scratch reg (%d).\n", r);
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return r;
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}
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WREG32(scratch, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 11);
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kiq_ring->ready = true;
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r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
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if (r) {
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DRM_ERROR("Failed to lock KIQ (%d).\n", r);
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amdgpu_gfx_scratch_free(adev, scratch);
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return r;
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}
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/* set resources */
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@ -4665,25 +4657,12 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
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amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
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amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
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}
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/* write to scratch for completion */
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
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amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
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amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
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amdgpu_ring_commit(kiq_ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(scratch);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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r = amdgpu_ring_test_ring(kiq_ring);
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if (r) {
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DRM_ERROR("KCQ enable failed\n");
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kiq_ring->ready = false;
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}
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if (i >= adev->usec_timeout) {
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DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
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scratch, tmp);
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r = -EINVAL;
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}
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amdgpu_gfx_scratch_free(adev, scratch);
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return r;
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}
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@ -5014,15 +4993,6 @@ static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
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if (r)
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goto done;
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/* Test KIQ */
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ring = &adev->gfx.kiq.ring;
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ring->ready = true;
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r = amdgpu_ring_test_ring(ring);
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if (r) {
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ring->ready = false;
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goto done;
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}
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/* Test KCQs */
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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ring = &adev->gfx.compute_ring[i];
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@ -5092,23 +5062,11 @@ static int gfx_v8_0_hw_init(void *handle)
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static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = kiq_ring->adev;
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uint32_t scratch, tmp = 0;
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int r, i;
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int r;
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r = amdgpu_gfx_scratch_get(adev, &scratch);
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if (r) {
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DRM_ERROR("Failed to get scratch reg (%d).\n", r);
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return r;
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}
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WREG32(scratch, 0xCAFEDEAD);
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r = amdgpu_ring_alloc(kiq_ring, 10);
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if (r) {
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r = amdgpu_ring_alloc(kiq_ring, 6);
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if (r)
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DRM_ERROR("Failed to lock KIQ (%d).\n", r);
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amdgpu_gfx_scratch_free(adev, scratch);
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return r;
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}
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/* unmap queues */
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
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@ -5121,23 +5079,11 @@ static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring
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amdgpu_ring_write(kiq_ring, 0);
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amdgpu_ring_write(kiq_ring, 0);
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amdgpu_ring_write(kiq_ring, 0);
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/* write to scratch for completion */
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amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
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amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
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amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
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amdgpu_ring_commit(kiq_ring);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(scratch);
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if (tmp == 0xDEADBEEF)
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break;
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DRM_UDELAY(1);
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}
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if (i >= adev->usec_timeout) {
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DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
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r = -EINVAL;
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}
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amdgpu_gfx_scratch_free(adev, scratch);
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r = amdgpu_ring_test_ring(kiq_ring);
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if (r)
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DRM_ERROR("KCQ disable failed\n");
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return r;
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}
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