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[libata] sata_mv: Micro-optimization and cleanups
* Micro-optimization in the EDMA interrupt handling code * s/EDMA_ERR_CRBQ_PAR/EDMA_ERR_CRQB_PAR/ * Document EDMA Error Interrupt Cause register bits Signed-off-by: Jeff Garzik <jeff@garzik.org>
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1 changed files with 31 additions and 34 deletions
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@ -227,26 +227,26 @@ enum {
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EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
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EDMA_ERR_IRQ_MASK_OFS = 0xc,
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EDMA_ERR_D_PAR = (1 << 0),
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EDMA_ERR_PRD_PAR = (1 << 1),
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EDMA_ERR_DEV = (1 << 2),
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EDMA_ERR_DEV_DCON = (1 << 3),
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EDMA_ERR_DEV_CON = (1 << 4),
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EDMA_ERR_SERR = (1 << 5),
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EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
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EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
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EDMA_ERR_DEV = (1 << 2), /* device error */
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EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
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EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
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EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
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EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
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EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
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EDMA_ERR_BIST_ASYNC = (1 << 8),
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EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
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EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
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EDMA_ERR_CRBQ_PAR = (1 << 9),
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EDMA_ERR_CRPB_PAR = (1 << 10),
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EDMA_ERR_INTRL_PAR = (1 << 11),
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EDMA_ERR_IORDY = (1 << 12),
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EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
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EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
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EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
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EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
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EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
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EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
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EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
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EDMA_ERR_LNK_DATA_RX = (0xf << 17),
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EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
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EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
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EDMA_ERR_TRANS_PROTO = (1 << 31),
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EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
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EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
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EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
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EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
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EDMA_ERR_OVERRUN_5 = (1 << 5),
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EDMA_ERR_UNDERRUN_5 = (1 << 6),
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EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
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@ -255,7 +255,7 @@ enum {
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EDMA_ERR_DEV_CON |
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EDMA_ERR_SERR |
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EDMA_ERR_SELF_DIS |
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EDMA_ERR_CRBQ_PAR |
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EDMA_ERR_CRQB_PAR |
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EDMA_ERR_CRPB_PAR |
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EDMA_ERR_INTRL_PAR |
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EDMA_ERR_IORDY |
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@ -270,7 +270,7 @@ enum {
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EDMA_ERR_OVERRUN_5 |
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EDMA_ERR_UNDERRUN_5 |
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EDMA_ERR_SELF_DIS_5 |
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EDMA_ERR_CRBQ_PAR |
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EDMA_ERR_CRQB_PAR |
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EDMA_ERR_CRPB_PAR |
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EDMA_ERR_INTRL_PAR |
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EDMA_ERR_IORDY,
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@ -1393,7 +1393,7 @@ static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
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if (edma_err_cause & EDMA_ERR_DEV)
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err_mask |= AC_ERR_DEV;
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if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
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EDMA_ERR_CRBQ_PAR | EDMA_ERR_CRPB_PAR |
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EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
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EDMA_ERR_INTRL_PAR)) {
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err_mask |= AC_ERR_ATA_BUS;
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action |= ATA_EH_HARDRESET;
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@ -1489,33 +1489,30 @@ static void mv_intr_edma(struct ata_port *ap)
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while (1) {
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u16 status;
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unsigned int tag;
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/* get s/w response queue last-read pointer, and compare */
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out_index = pp->resp_idx & MV_MAX_Q_DEPTH_MASK;
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if (in_index == out_index)
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break;
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/* 50xx: get active ATA command */
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if (IS_GEN_I(hpriv))
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qc = ata_qc_from_tag(ap, ap->active_tag);
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tag = ap->active_tag;
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/* 60xx: get active ATA command via tag, to enable support
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* for queueing. this works transparently for queued and
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* non-queued modes.
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/* Gen II/IIE: get active ATA command via tag, to enable
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* support for queueing. this works transparently for
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* queued and non-queued modes.
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*/
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else {
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unsigned int tag;
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else if (IS_GEN_II(hpriv))
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tag = (le16_to_cpu(pp->crpb[out_index].id)
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>> CRPB_IOID_SHIFT_6) & 0x3f;
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if (IS_GEN_II(hpriv))
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tag = (le16_to_cpu(pp->crpb[out_index].id)
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>> CRPB_IOID_SHIFT_6) & 0x3f;
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else
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tag = (le16_to_cpu(pp->crpb[out_index].id)
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>> CRPB_IOID_SHIFT_7) & 0x3f;
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else /* IS_GEN_IIE */
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tag = (le16_to_cpu(pp->crpb[out_index].id)
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>> CRPB_IOID_SHIFT_7) & 0x3f;
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qc = ata_qc_from_tag(ap, tag);
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}
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qc = ata_qc_from_tag(ap, tag);
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/* lower 8 bits of status are EDMA_ERR_IRQ_CAUSE_OFS
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* bits (WARNING: might not necessarily be associated
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