smartpqi: initial commit of Microsemi smartpqi driver

This initial commit contains Microsemi's smartpqi module.

[mkp: Minor tweaks to apply to 4.9/scsi-queue]

Reviewed-by: Scott Benesh <scott.benesh@microsemi.com>
Reviewed-by: Kevin Barnett <kevin.barnett@microsemi.com>
Signed-off-by: Kevin Barnett <kevin.barnett@microsemi.com>
Signed-off-by: Don Brace <don.brace@microsemi.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de>
Reviewed-by: Ewan D. Milne <emilne@redhat.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Kevin Barnett 2016-06-27 16:41:00 -05:00 committed by Martin K. Petersen
parent 1d48390117
commit 6c223761eb
10 changed files with 8281 additions and 0 deletions

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@ -7819,6 +7819,17 @@ W: http://www.melexis.com
S: Supported
F: drivers/iio/temperature/mlx90614.c
MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi)
M: Don Brace <don.brace@microsemi.com>
L: esc.storagedev@microsemi.com
L: linux-scsi@vger.kernel.org
S: Supported
F: drivers/scsi/smartpqi/smartpqi*.[ch]
F: drivers/scsi/smartpqi/Kconfig
F: drivers/scsi/smartpqi/Makefile
F: include/linux/cciss*.h
F: include/uapi/linux/cciss*.h
MN88472 MEDIA DRIVER
M: Antti Palosaari <crope@iki.fi>
L: linux-media@vger.kernel.org

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@ -540,6 +540,7 @@ config SCSI_ARCMSR
source "drivers/scsi/esas2r/Kconfig"
source "drivers/scsi/megaraid/Kconfig.megaraid"
source "drivers/scsi/mpt3sas/Kconfig"
source "drivers/scsi/smartpqi/Kconfig"
source "drivers/scsi/ufs/Kconfig"
config SCSI_HPTIOP

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@ -94,6 +94,7 @@ obj-$(CONFIG_SCSI_PAS16) += pas16.o
obj-$(CONFIG_SCSI_T128) += t128.o
obj-$(CONFIG_SCSI_DMX3191D) += dmx3191d.o
obj-$(CONFIG_SCSI_HPSA) += hpsa.o
obj-$(CONFIG_SCSI_SMARTPQI) += smartpqi/
obj-$(CONFIG_SCSI_DTC3280) += dtc.o
obj-$(CONFIG_SCSI_SYM53C8XX_2) += sym53c8xx_2/
obj-$(CONFIG_SCSI_ZALON) += zalon7xx.o

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@ -0,0 +1,50 @@
#
# Kernel configuration file for the SMARTPQI
#
# Copyright (c) 2016 Microsemi Corporation
# Copyright (c) 2016 PMC-Sierra, Inc.
# (mailto:esc.storagedev@microsemi.com)
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# as published by the Free Software Foundation; version 2
# of the License.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# NO WARRANTY
# THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
# CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
# LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
# MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
# solely responsible for determining the appropriateness of using and
# distributing the Program and assumes all risks associated with its
# exercise of rights under this Agreement, including but not limited to
# the risks and costs of program errors, damage to or loss of data,
# programs or equipment, and unavailability or interruption of operations.
# DISCLAIMER OF LIABILITY
# NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
# USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
# HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
config SCSI_SMARTPQI
tristate "Microsemi PQI Driver"
default n
depends on PCI && SCSI && !S390
select SCSI_SAS_ATTRS
select RAID_ATTRS
---help---
This driver supports Microsemi PQI controllers.
<http://www.microsemi.com>
To compile this driver as a module, choose M here: the
module will be called smartpqi

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@ -0,0 +1,3 @@
ccflags-y += -I.
obj-m += smartpqi.o
smartpqi-objs := smartpqi_init.o smartpqi_sis.o smartpqi_sas_transport.o

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@ -0,0 +1,350 @@
/*
* driver for Microsemi PQI-based storage controllers
* Copyright (c) 2016 Microsemi Corporation
* Copyright (c) 2016 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more details.
*
* Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
*
*/
#include <linux/kernel.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_transport_sas.h>
#include "smartpqi.h"
static struct pqi_sas_phy *pqi_alloc_sas_phy(struct pqi_sas_port *pqi_sas_port)
{
struct pqi_sas_phy *pqi_sas_phy;
struct sas_phy *phy;
pqi_sas_phy = kzalloc(sizeof(*pqi_sas_phy), GFP_KERNEL);
if (!pqi_sas_phy)
return NULL;
phy = sas_phy_alloc(pqi_sas_port->parent_node->parent_dev,
pqi_sas_port->next_phy_index);
if (!phy) {
kfree(pqi_sas_phy);
return NULL;
}
pqi_sas_port->next_phy_index++;
pqi_sas_phy->phy = phy;
pqi_sas_phy->parent_port = pqi_sas_port;
return pqi_sas_phy;
}
static void pqi_free_sas_phy(struct pqi_sas_phy *pqi_sas_phy)
{
struct sas_phy *phy = pqi_sas_phy->phy;
sas_port_delete_phy(pqi_sas_phy->parent_port->port, phy);
sas_phy_free(phy);
if (pqi_sas_phy->added_to_port)
list_del(&pqi_sas_phy->phy_list_entry);
kfree(pqi_sas_phy);
}
static int pqi_sas_port_add_phy(struct pqi_sas_phy *pqi_sas_phy)
{
int rc;
struct pqi_sas_port *pqi_sas_port;
struct sas_phy *phy;
struct sas_identify *identify;
pqi_sas_port = pqi_sas_phy->parent_port;
phy = pqi_sas_phy->phy;
identify = &phy->identify;
memset(identify, 0, sizeof(*identify));
identify->sas_address = pqi_sas_port->sas_address;
identify->device_type = SAS_END_DEVICE;
identify->initiator_port_protocols = SAS_PROTOCOL_STP;
identify->target_port_protocols = SAS_PROTOCOL_STP;
phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
rc = sas_phy_add(pqi_sas_phy->phy);
if (rc)
return rc;
sas_port_add_phy(pqi_sas_port->port, pqi_sas_phy->phy);
list_add_tail(&pqi_sas_phy->phy_list_entry,
&pqi_sas_port->phy_list_head);
pqi_sas_phy->added_to_port = true;
return 0;
}
static int pqi_sas_port_add_rphy(struct pqi_sas_port *pqi_sas_port,
struct sas_rphy *rphy)
{
struct sas_identify *identify;
identify = &rphy->identify;
identify->sas_address = pqi_sas_port->sas_address;
identify->initiator_port_protocols = SAS_PROTOCOL_STP;
identify->target_port_protocols = SAS_PROTOCOL_STP;
return sas_rphy_add(rphy);
}
static struct pqi_sas_port *pqi_alloc_sas_port(
struct pqi_sas_node *pqi_sas_node, u64 sas_address)
{
int rc;
struct pqi_sas_port *pqi_sas_port;
struct sas_port *port;
pqi_sas_port = kzalloc(sizeof(*pqi_sas_port), GFP_KERNEL);
if (!pqi_sas_port)
return NULL;
INIT_LIST_HEAD(&pqi_sas_port->phy_list_head);
pqi_sas_port->parent_node = pqi_sas_node;
port = sas_port_alloc_num(pqi_sas_node->parent_dev);
if (!port)
goto free_pqi_port;
rc = sas_port_add(port);
if (rc)
goto free_sas_port;
pqi_sas_port->port = port;
pqi_sas_port->sas_address = sas_address;
list_add_tail(&pqi_sas_port->port_list_entry,
&pqi_sas_node->port_list_head);
return pqi_sas_port;
free_sas_port:
sas_port_free(port);
free_pqi_port:
kfree(pqi_sas_port);
return NULL;
}
static void pqi_free_sas_port(struct pqi_sas_port *pqi_sas_port)
{
struct pqi_sas_phy *pqi_sas_phy;
struct pqi_sas_phy *next;
list_for_each_entry_safe(pqi_sas_phy, next,
&pqi_sas_port->phy_list_head, phy_list_entry)
pqi_free_sas_phy(pqi_sas_phy);
sas_port_delete(pqi_sas_port->port);
list_del(&pqi_sas_port->port_list_entry);
kfree(pqi_sas_port);
}
static struct pqi_sas_node *pqi_alloc_sas_node(struct device *parent_dev)
{
struct pqi_sas_node *pqi_sas_node;
pqi_sas_node = kzalloc(sizeof(*pqi_sas_node), GFP_KERNEL);
if (pqi_sas_node) {
pqi_sas_node->parent_dev = parent_dev;
INIT_LIST_HEAD(&pqi_sas_node->port_list_head);
}
return pqi_sas_node;
}
static void pqi_free_sas_node(struct pqi_sas_node *pqi_sas_node)
{
struct pqi_sas_port *pqi_sas_port;
struct pqi_sas_port *next;
if (!pqi_sas_node)
return;
list_for_each_entry_safe(pqi_sas_port, next,
&pqi_sas_node->port_list_head, port_list_entry)
pqi_free_sas_port(pqi_sas_port);
kfree(pqi_sas_node);
}
struct pqi_scsi_dev *pqi_find_device_by_sas_rphy(
struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy)
{
struct pqi_scsi_dev *device;
list_for_each_entry(device, &ctrl_info->scsi_device_list,
scsi_device_list_entry) {
if (!device->sas_port)
continue;
if (device->sas_port->rphy == rphy)
return device;
}
return NULL;
}
int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info)
{
int rc;
struct device *parent_dev;
struct pqi_sas_node *pqi_sas_node;
struct pqi_sas_port *pqi_sas_port;
struct pqi_sas_phy *pqi_sas_phy;
parent_dev = &shost->shost_gendev;
pqi_sas_node = pqi_alloc_sas_node(parent_dev);
if (!pqi_sas_node)
return -ENOMEM;
pqi_sas_port = pqi_alloc_sas_port(pqi_sas_node, ctrl_info->sas_address);
if (!pqi_sas_port) {
rc = -ENODEV;
goto free_sas_node;
}
pqi_sas_phy = pqi_alloc_sas_phy(pqi_sas_port);
if (!pqi_sas_phy) {
rc = -ENODEV;
goto free_sas_port;
}
rc = pqi_sas_port_add_phy(pqi_sas_phy);
if (rc)
goto free_sas_phy;
ctrl_info->sas_host = pqi_sas_node;
return 0;
free_sas_phy:
pqi_free_sas_phy(pqi_sas_phy);
free_sas_port:
pqi_free_sas_port(pqi_sas_port);
free_sas_node:
pqi_free_sas_node(pqi_sas_node);
return rc;
}
void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info)
{
pqi_free_sas_node(ctrl_info->sas_host);
}
int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
struct pqi_scsi_dev *device)
{
int rc;
struct pqi_sas_port *pqi_sas_port;
struct sas_rphy *rphy;
pqi_sas_port = pqi_alloc_sas_port(pqi_sas_node, device->sas_address);
if (!pqi_sas_port)
return -ENOMEM;
rphy = sas_end_device_alloc(pqi_sas_port->port);
if (!rphy) {
rc = -ENODEV;
goto free_sas_port;
}
pqi_sas_port->rphy = rphy;
device->sas_port = pqi_sas_port;
rc = pqi_sas_port_add_rphy(pqi_sas_port, rphy);
if (rc)
goto free_sas_port;
return 0;
free_sas_port:
pqi_free_sas_port(pqi_sas_port);
device->sas_port = NULL;
return rc;
}
void pqi_remove_sas_device(struct pqi_scsi_dev *device)
{
if (device->sas_port) {
pqi_free_sas_port(device->sas_port);
device->sas_port = NULL;
}
}
static int pqi_sas_get_linkerrors(struct sas_phy *phy)
{
return 0;
}
static int pqi_sas_get_enclosure_identifier(struct sas_rphy *rphy,
u64 *identifier)
{
return 0;
}
static int pqi_sas_get_bay_identifier(struct sas_rphy *rphy)
{
return -ENXIO;
}
static int pqi_sas_phy_reset(struct sas_phy *phy, int hard_reset)
{
return 0;
}
static int pqi_sas_phy_enable(struct sas_phy *phy, int enable)
{
return 0;
}
static int pqi_sas_phy_setup(struct sas_phy *phy)
{
return 0;
}
static void pqi_sas_phy_release(struct sas_phy *phy)
{
}
static int pqi_sas_phy_speed(struct sas_phy *phy,
struct sas_phy_linkrates *rates)
{
return -EINVAL;
}
/* SMP = Serial Management Protocol */
static int pqi_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
struct request *req)
{
return -EINVAL;
}
struct sas_function_template pqi_sas_transport_functions = {
.get_linkerrors = pqi_sas_get_linkerrors,
.get_enclosure_identifier = pqi_sas_get_enclosure_identifier,
.get_bay_identifier = pqi_sas_get_bay_identifier,
.phy_reset = pqi_sas_phy_reset,
.phy_enable = pqi_sas_phy_enable,
.phy_setup = pqi_sas_phy_setup,
.phy_release = pqi_sas_phy_release,
.set_phy_speed = pqi_sas_phy_speed,
.smp_handler = pqi_sas_smp_handler,
};

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@ -0,0 +1,394 @@
/*
* driver for Microsemi PQI-based storage controllers
* Copyright (c) 2016 Microsemi Corporation
* Copyright (c) 2016 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more details.
*
* Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <scsi/scsi_device.h>
#include <asm/unaligned.h>
#include "smartpqi.h"
#include "smartpqi_sis.h"
/* legacy SIS interface commands */
#define SIS_CMD_GET_ADAPTER_PROPERTIES 0x19
#define SIS_CMD_INIT_BASE_STRUCT_ADDRESS 0x1b
#define SIS_CMD_GET_PQI_CAPABILITIES 0x3000
/* for submission of legacy SIS commands */
#define SIS_REENABLE_SIS_MODE 0x1
#define SIS_ENABLE_MSIX 0x40
#define SIS_SOFT_RESET 0x100
#define SIS_CMD_READY 0x200
#define SIS_CMD_COMPLETE 0x1000
#define SIS_CLEAR_CTRL_TO_HOST_DOORBELL 0x1000
#define SIS_CMD_STATUS_SUCCESS 0x1
#define SIS_CMD_COMPLETE_TIMEOUT_SECS 30
#define SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS 10
/* used with SIS_CMD_GET_ADAPTER_PROPERTIES command */
#define SIS_EXTENDED_PROPERTIES_SUPPORTED 0x800000
#define SIS_SMARTARRAY_FEATURES_SUPPORTED 0x2
#define SIS_PQI_MODE_SUPPORTED 0x4
#define SIS_REQUIRED_EXTENDED_PROPERTIES \
(SIS_SMARTARRAY_FEATURES_SUPPORTED | SIS_PQI_MODE_SUPPORTED)
/* used with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
#define SIS_BASE_STRUCT_REVISION 9
#define SIS_BASE_STRUCT_ALIGNMENT 16
#define SIS_CTRL_KERNEL_UP 0x80
#define SIS_CTRL_KERNEL_PANIC 0x100
#define SIS_CTRL_READY_TIMEOUT_SECS 30
#define SIS_CTRL_READY_POLL_INTERVAL_MSECS 10
#pragma pack(1)
/* for use with SIS_CMD_INIT_BASE_STRUCT_ADDRESS command */
struct sis_base_struct {
__le32 revision; /* revision of this structure */
__le32 flags; /* reserved */
__le32 error_buffer_paddr_low; /* lower 32 bits of physical memory */
/* buffer for PQI error response */
/* data */
__le32 error_buffer_paddr_high; /* upper 32 bits of physical */
/* memory buffer for PQI */
/* error response data */
__le32 error_buffer_element_length; /* length of each PQI error */
/* response buffer element */
/* in bytes */
__le32 error_buffer_num_elements; /* total number of PQI error */
/* response buffers available */
};
#pragma pack()
int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info)
{
unsigned long timeout;
u32 status;
timeout = (SIS_CTRL_READY_TIMEOUT_SECS * HZ) + jiffies;
while (1) {
status = readl(&ctrl_info->registers->sis_firmware_status);
if (status != ~0) {
if (status & SIS_CTRL_KERNEL_PANIC) {
dev_err(&ctrl_info->pci_dev->dev,
"controller is offline: status code 0x%x\n",
readl(
&ctrl_info->registers->sis_mailbox[7]));
return -ENODEV;
}
if (status & SIS_CTRL_KERNEL_UP)
break;
}
if (time_after(jiffies, timeout))
return -ETIMEDOUT;
msleep(SIS_CTRL_READY_POLL_INTERVAL_MSECS);
}
return 0;
}
bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info)
{
bool running;
u32 status;
status = readl(&ctrl_info->registers->sis_firmware_status);
if (status & SIS_CTRL_KERNEL_PANIC)
running = false;
else
running = true;
if (!running)
dev_err(&ctrl_info->pci_dev->dev,
"controller is offline: status code 0x%x\n",
readl(&ctrl_info->registers->sis_mailbox[7]));
return running;
}
/* used for passing command parameters/results when issuing SIS commands */
struct sis_sync_cmd_params {
u32 mailbox[6]; /* mailboxes 0-5 */
};
static int sis_send_sync_cmd(struct pqi_ctrl_info *ctrl_info,
u32 cmd, struct sis_sync_cmd_params *params)
{
struct pqi_ctrl_registers __iomem *registers;
unsigned int i;
unsigned long timeout;
u32 doorbell;
u32 cmd_status;
registers = ctrl_info->registers;
/* Write the command to mailbox 0. */
writel(cmd, &registers->sis_mailbox[0]);
/*
* Write the command parameters to mailboxes 1-4 (mailbox 5 is not used
* when sending a command to the controller).
*/
for (i = 1; i <= 4; i++)
writel(params->mailbox[i], &registers->sis_mailbox[i]);
/* Clear the command doorbell. */
writel(SIS_CLEAR_CTRL_TO_HOST_DOORBELL,
&registers->sis_ctrl_to_host_doorbell_clear);
/* Disable doorbell interrupts by masking all interrupts. */
writel(~0, &registers->sis_interrupt_mask);
/*
* Force the completion of the interrupt mask register write before
* submitting the command.
*/
readl(&registers->sis_interrupt_mask);
/* Submit the command to the controller. */
writel(SIS_CMD_READY, &registers->sis_host_to_ctrl_doorbell);
/*
* Poll for command completion. Note that the call to msleep() is at
* the top of the loop in order to give the controller time to start
* processing the command before we start polling.
*/
timeout = (SIS_CMD_COMPLETE_TIMEOUT_SECS * HZ) + jiffies;
while (1) {
msleep(SIS_CMD_COMPLETE_POLL_INTERVAL_MSECS);
doorbell = readl(&registers->sis_ctrl_to_host_doorbell);
if (doorbell & SIS_CMD_COMPLETE)
break;
if (time_after(jiffies, timeout))
return -ETIMEDOUT;
}
/* Read the command status from mailbox 0. */
cmd_status = readl(&registers->sis_mailbox[0]);
if (cmd_status != SIS_CMD_STATUS_SUCCESS) {
dev_err(&ctrl_info->pci_dev->dev,
"SIS command failed for command 0x%x: status = 0x%x\n",
cmd, cmd_status);
return -EINVAL;
}
/*
* The command completed successfully, so save the command status and
* read the values returned in mailboxes 1-5.
*/
params->mailbox[0] = cmd_status;
for (i = 1; i < ARRAY_SIZE(params->mailbox); i++)
params->mailbox[i] = readl(&registers->sis_mailbox[i]);
return 0;
}
/*
* This function verifies that we are talking to a controller that speaks PQI.
*/
int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info)
{
int rc;
u32 properties;
u32 extended_properties;
struct sis_sync_cmd_params params;
memset(&params, 0, sizeof(params));
rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_ADAPTER_PROPERTIES,
&params);
if (rc)
return rc;
properties = params.mailbox[1];
if (!(properties & SIS_EXTENDED_PROPERTIES_SUPPORTED))
return -ENODEV;
extended_properties = params.mailbox[4];
if ((extended_properties & SIS_REQUIRED_EXTENDED_PROPERTIES) !=
SIS_REQUIRED_EXTENDED_PROPERTIES)
return -ENODEV;
return 0;
}
int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info)
{
int rc;
struct sis_sync_cmd_params params;
memset(&params, 0, sizeof(params));
rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_GET_PQI_CAPABILITIES,
&params);
if (rc)
return rc;
ctrl_info->max_sg_entries = params.mailbox[1];
ctrl_info->max_transfer_size = params.mailbox[2];
ctrl_info->max_outstanding_requests = params.mailbox[3];
ctrl_info->config_table_offset = params.mailbox[4];
ctrl_info->config_table_length = params.mailbox[5];
return 0;
}
int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info)
{
int rc;
void *base_struct_unaligned;
struct sis_base_struct *base_struct;
struct sis_sync_cmd_params params;
unsigned long error_buffer_paddr;
dma_addr_t bus_address;
base_struct_unaligned = kzalloc(sizeof(*base_struct)
+ SIS_BASE_STRUCT_ALIGNMENT - 1, GFP_KERNEL);
if (!base_struct_unaligned)
return -ENOMEM;
base_struct = PTR_ALIGN(base_struct_unaligned,
SIS_BASE_STRUCT_ALIGNMENT);
error_buffer_paddr = (unsigned long)ctrl_info->error_buffer_dma_handle;
put_unaligned_le32(SIS_BASE_STRUCT_REVISION, &base_struct->revision);
put_unaligned_le32(lower_32_bits(error_buffer_paddr),
&base_struct->error_buffer_paddr_low);
put_unaligned_le32(upper_32_bits(error_buffer_paddr),
&base_struct->error_buffer_paddr_high);
put_unaligned_le32(PQI_ERROR_BUFFER_ELEMENT_LENGTH,
&base_struct->error_buffer_element_length);
put_unaligned_le32(ctrl_info->max_io_slots,
&base_struct->error_buffer_num_elements);
bus_address = pci_map_single(ctrl_info->pci_dev, base_struct,
sizeof(*base_struct), PCI_DMA_TODEVICE);
if (pci_dma_mapping_error(ctrl_info->pci_dev, bus_address)) {
rc = -ENOMEM;
goto out;
}
memset(&params, 0, sizeof(params));
params.mailbox[1] = lower_32_bits((u64)bus_address);
params.mailbox[2] = upper_32_bits((u64)bus_address);
params.mailbox[3] = sizeof(*base_struct);
rc = sis_send_sync_cmd(ctrl_info, SIS_CMD_INIT_BASE_STRUCT_ADDRESS,
&params);
pci_unmap_single(ctrl_info->pci_dev, bus_address, sizeof(*base_struct),
PCI_DMA_TODEVICE);
out:
kfree(base_struct_unaligned);
return rc;
}
/* Enable MSI-X interrupts on the controller. */
void sis_enable_msix(struct pqi_ctrl_info *ctrl_info)
{
u32 doorbell_register;
doorbell_register =
readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
doorbell_register |= SIS_ENABLE_MSIX;
writel(doorbell_register,
&ctrl_info->registers->sis_host_to_ctrl_doorbell);
}
/* Disable MSI-X interrupts on the controller. */
void sis_disable_msix(struct pqi_ctrl_info *ctrl_info)
{
u32 doorbell_register;
doorbell_register =
readl(&ctrl_info->registers->sis_host_to_ctrl_doorbell);
doorbell_register &= ~SIS_ENABLE_MSIX;
writel(doorbell_register,
&ctrl_info->registers->sis_host_to_ctrl_doorbell);
}
void sis_soft_reset(struct pqi_ctrl_info *ctrl_info)
{
writel(SIS_SOFT_RESET,
&ctrl_info->registers->sis_host_to_ctrl_doorbell);
}
#define SIS_MODE_READY_TIMEOUT_SECS 30
int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info)
{
int rc;
unsigned long timeout;
struct pqi_ctrl_registers __iomem *registers;
u32 doorbell;
registers = ctrl_info->registers;
writel(SIS_REENABLE_SIS_MODE,
&registers->sis_host_to_ctrl_doorbell);
rc = 0;
timeout = (SIS_MODE_READY_TIMEOUT_SECS * HZ) + jiffies;
while (1) {
doorbell = readl(&registers->sis_ctrl_to_host_doorbell);
if ((doorbell & SIS_REENABLE_SIS_MODE) == 0)
break;
if (time_after(jiffies, timeout)) {
rc = -ETIMEDOUT;
break;
}
}
if (rc)
dev_err(&ctrl_info->pci_dev->dev,
"re-enabling SIS mode failed\n");
return rc;
}
static void __attribute__((unused)) verify_structures(void)
{
BUILD_BUG_ON(offsetof(struct sis_base_struct,
revision) != 0x0);
BUILD_BUG_ON(offsetof(struct sis_base_struct,
flags) != 0x4);
BUILD_BUG_ON(offsetof(struct sis_base_struct,
error_buffer_paddr_low) != 0x8);
BUILD_BUG_ON(offsetof(struct sis_base_struct,
error_buffer_paddr_high) != 0xc);
BUILD_BUG_ON(offsetof(struct sis_base_struct,
error_buffer_element_length) != 0x10);
BUILD_BUG_ON(offsetof(struct sis_base_struct,
error_buffer_num_elements) != 0x14);
BUILD_BUG_ON(sizeof(struct sis_base_struct) != 0x18);
}

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@ -0,0 +1,32 @@
/*
* driver for Microsemi PQI-based storage controllers
* Copyright (c) 2016 Microsemi Corporation
* Copyright (c) 2016 PMC-Sierra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more details.
*
* Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
*
*/
#if !defined(_SMARTPQI_SIS_H)
#define _SMARTPQI_SIS_H
int sis_wait_for_ctrl_ready(struct pqi_ctrl_info *ctrl_info);
bool sis_is_firmware_running(struct pqi_ctrl_info *ctrl_info);
int sis_get_ctrl_properties(struct pqi_ctrl_info *ctrl_info);
int sis_get_pqi_capabilities(struct pqi_ctrl_info *ctrl_info);
int sis_init_base_struct_addr(struct pqi_ctrl_info *ctrl_info);
void sis_enable_msix(struct pqi_ctrl_info *ctrl_info);
void sis_disable_msix(struct pqi_ctrl_info *ctrl_info);
void sis_soft_reset(struct pqi_ctrl_info *ctrl_info);
int sis_reenable_sis_mode(struct pqi_ctrl_info *ctrl_info);
#endif /* _SMARTPQI_SIS_H */