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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
Blackfin: add support for cpufreq on SMP systems
Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
parent
3b82790c12
commit
6c2b7072a7
4 changed files with 108 additions and 73 deletions
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@ -1237,7 +1237,6 @@ config PM_BFIN_WAKE_GP
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endmenu
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menu "CPU Frequency scaling"
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depends on !SMP
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source "drivers/cpufreq/Kconfig"
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@ -23,9 +23,7 @@
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*/
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#ifndef CONFIG_CPU_FREQ
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#define TIME_SCALE 1
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#define __bfin_cycles_off (0)
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#define __bfin_cycles_mod (0)
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# define TIME_SCALE 1
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#else
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/*
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* Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
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@ -33,8 +31,11 @@
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* adjust the Core Timer Presale Register. This way we don't lose time.
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*/
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#define TIME_SCALE 4
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# ifdef CONFIG_CYCLES_CLOCKSOURCE
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extern unsigned long long __bfin_cycles_off;
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extern unsigned int __bfin_cycles_mod;
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# endif
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#endif
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#if defined(CONFIG_TICKSOURCE_CORETMR)
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@ -51,7 +51,11 @@
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static notrace cycle_t bfin_read_cycles(struct clocksource *cs)
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{
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#ifdef CONFIG_CPU_FREQ
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return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod);
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#else
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return get_cycles();
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#endif
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}
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static struct clocksource bfin_cs_cycles = {
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@ -15,6 +15,8 @@
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#include <asm/time.h>
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#include <asm/dpmc.h>
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#define CPUFREQ_CPU 0
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/* this is the table of CCLK frequencies, in Hz */
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/* .index is the entry in the auxillary dpm_state_table[] */
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static struct cpufreq_frequency_table bfin_freq_table[] = {
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@ -41,84 +43,24 @@ static struct bfin_dpm_state {
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unsigned int tscale; /* change the divider on the core timer interrupt */
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} dpm_state_table[3];
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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/*
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normalized to maximum frequncy offset for CYCLES,
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used in time-ts cycles clock source, but could be used
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somewhere also.
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* normalized to maximum frequncy offset for CYCLES,
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* used in time-ts cycles clock source, but could be used
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* somewhere also.
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*/
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unsigned long long __bfin_cycles_off;
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unsigned int __bfin_cycles_mod;
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#endif
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/**************************************************************************/
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static unsigned int bfin_getfreq_khz(unsigned int cpu)
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{
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/* The driver only support single cpu */
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if (cpu != 0)
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return -1;
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return get_cclk() / 1000;
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}
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static int bfin_target(struct cpufreq_policy *policy,
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unsigned int target_freq, unsigned int relation)
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{
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unsigned int index, plldiv, tscale;
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unsigned long flags, cclk_hz;
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struct cpufreq_freqs freqs;
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cycles_t cycles;
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if (cpufreq_frequency_table_target(policy, bfin_freq_table,
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target_freq, relation, &index))
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return -EINVAL;
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cclk_hz = bfin_freq_table[index].frequency;
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freqs.old = bfin_getfreq_khz(0);
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freqs.new = cclk_hz;
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freqs.cpu = 0;
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pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
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cclk_hz, target_freq, freqs.old);
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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local_irq_save_hw(flags);
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plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
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tscale = dpm_state_table[index].tscale;
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bfin_write_PLL_DIV(plldiv);
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/* we have to adjust the core timer, because it is using cclk */
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bfin_write_TSCALE(tscale);
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cycles = get_cycles();
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SSYNC();
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cycles += 10; /* ~10 cycles we lose after get_cycles() */
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__bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index);
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__bfin_cycles_mod = index;
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local_irq_restore_hw(flags);
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/* TODO: just test case for cycles clock source, remove later */
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pr_debug("cpufreq: done\n");
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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return 0;
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}
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static int bfin_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, bfin_freq_table);
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}
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static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
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static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
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{
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unsigned long cclk, sclk, csel, min_cclk;
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unsigned long csel, min_cclk;
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int index;
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if (policy->cpu != 0)
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return -EINVAL;
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cclk = get_cclk() / 1000;
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sclk = get_sclk() / 1000;
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/* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
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#if ANOMALY_05000273 || ANOMALY_05000274 || \
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(!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
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min_cclk = sclk * 2;
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@ -137,10 +79,99 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
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dpm_state_table[index].csel,
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dpm_state_table[index].tscale);
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}
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return;
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}
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static void bfin_adjust_core_timer(void *info)
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{
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unsigned int tscale;
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unsigned int index = *(unsigned int *)info;
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/* we have to adjust the core timer, because it is using cclk */
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tscale = dpm_state_table[index].tscale;
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bfin_write_TSCALE(tscale);
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return;
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}
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static unsigned int bfin_getfreq_khz(unsigned int cpu)
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{
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/* Both CoreA/B have the same core clock */
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return get_cclk() / 1000;
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}
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static int bfin_target(struct cpufreq_policy *poli,
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unsigned int target_freq, unsigned int relation)
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{
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unsigned int index, plldiv, cpu;
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unsigned long flags, cclk_hz;
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struct cpufreq_freqs freqs;
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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cycles_t cycles;
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#endif
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for_each_online_cpu(cpu) {
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struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);
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if (!policy)
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continue;
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if (cpufreq_frequency_table_target(policy, bfin_freq_table,
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target_freq, relation, &index))
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return -EINVAL;
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cclk_hz = bfin_freq_table[index].frequency;
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freqs.old = bfin_getfreq_khz(0);
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freqs.new = cclk_hz;
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freqs.cpu = cpu;
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pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
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cclk_hz, target_freq, freqs.old);
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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if (cpu == CPUFREQ_CPU) {
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local_irq_save_hw(flags);
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plldiv = (bfin_read_PLL_DIV() & SSEL) |
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dpm_state_table[index].csel;
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bfin_write_PLL_DIV(plldiv);
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on_each_cpu(bfin_adjust_core_timer, &index, 1);
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#if defined(CONFIG_CYCLES_CLOCKSOURCE)
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cycles = get_cycles();
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SSYNC();
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cycles += 10; /* ~10 cycles we lose after get_cycles() */
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__bfin_cycles_off +=
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(cycles << __bfin_cycles_mod) - (cycles << index);
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__bfin_cycles_mod = index;
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#endif
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local_irq_restore_hw(flags);
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}
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/* TODO: just test case for cycles clock source, remove later */
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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}
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pr_debug("cpufreq: done\n");
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return 0;
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}
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static int bfin_verify_speed(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, bfin_freq_table);
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}
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static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
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{
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unsigned long cclk, sclk;
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cclk = get_cclk() / 1000;
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sclk = get_sclk() / 1000;
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if (policy->cpu == CPUFREQ_CPU)
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bfin_init_tables(cclk, sclk);
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policy->cpuinfo.transition_latency = 50000; /* 50us assumed */
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/*Now ,only support one cpu */
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policy->cur = cclk;
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cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
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return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
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