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[ARM] Feroceon: speed up flushing of the entire cache
Flushing the L1 D cache with a test/clean/invalidate loop is very easy in software, but it is not the quickest way of doing it, as there is a lot of overhead involved in re-scanning the cache from the beginning every time we hit a dirty line. This patch makes proc-feroceon.S use "clean+invalidate by set/way" loops according to possible cache configuration of Feroceon CPUs (either direct-mapped or 4-way set associative). Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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1 changed files with 48 additions and 11 deletions
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@ -44,11 +44,31 @@
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*/
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#define CACHE_DLINESIZE 32
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.bss
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.align 3
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__cache_params_loc:
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.space 8
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.text
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__cache_params:
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.word __cache_params_loc
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/*
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* cpu_feroceon_proc_init()
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*/
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ENTRY(cpu_feroceon_proc_init)
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mrc p15, 0, r0, c0, c0, 1 @ read cache type register
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ldr r1, __cache_params
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mov r2, #(16 << 5)
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tst r0, #(1 << 16) @ get way
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mov r0, r0, lsr #18 @ get cache size order
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movne r3, #((4 - 1) << 30) @ 4-way
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and r0, r0, #0xf
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moveq r3, #0 @ 1-way
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mov r2, r2, lsl r0 @ actual cache size
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movne r2, r2, lsr #2 @ turned into # of sets
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sub r2, r2, #(1 << 5)
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stmia r1, {r2, r3}
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mov pc, lr
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/*
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@ -117,11 +137,19 @@ ENTRY(feroceon_flush_user_cache_all)
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*/
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ENTRY(feroceon_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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ldr r1, __cache_params
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ldmia r1, {r1, r3}
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1: orr ip, r1, r3
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2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
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subs ip, ip, #(1 << 30) @ next way
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bcs 2b
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subs r1, r1, #(1 << 5) @ next set
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bcs 1b
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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@ -138,7 +166,6 @@ __flush_whole_cache:
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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@ -152,6 +179,7 @@ ENTRY(feroceon_flush_user_cache_range)
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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@ -306,16 +334,25 @@ ENTRY(cpu_feroceon_dcache_clean_area)
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.align 5
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ENTRY(cpu_feroceon_switch_mm)
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#ifdef CONFIG_MMU
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mov ip, #0
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@ && 'Clean & Invalidate whole DCache'
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
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bne 1b
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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/*
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* Note: we wish to call __flush_whole_cache but we need to preserve
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* lr to do so. The only way without touching main memory is to
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* use r2 which is normally used to test the VM_EXEC flag, and
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* compensate locally for the skipped ops if it is not set.
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*/
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mov r2, lr @ abuse r2 to preserve lr
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bl __flush_whole_cache
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@ if r2 contains the VM_EXEC bit then the next 2 ops are done already
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tst r2, #VM_EXEC
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mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcreq p15, 0, ip, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mov pc, r2
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#else
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mov pc, lr
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#endif
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/*
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* cpu_feroceon_set_pte_ext(ptep, pte, ext)
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