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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-28 07:13:34 +00:00
mtd: spi-nor: atmel-quadspi: Remove unused code from atmel-quadspi driver
Code used for previous interface is no longer needed. This change just removes obsolete code. Suggested-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Piotr Bugalski <bugalski.piotr@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Piotr Bugalski
Mark Brown
parent
2d30ac5ed6
commit
6ca622c871
1 changed files with 0 additions and 388 deletions
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@ -29,14 +29,9 @@
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/spi-nor.h>
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#include <linux/platform_data/atmel.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <linux/gpio/consumer.h>
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#include <linux/spi/spi-mem.h>
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/* QSPI register offsets */
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@ -160,35 +155,9 @@ struct atmel_qspi {
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struct clk *clk;
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struct platform_device *pdev;
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u32 pending;
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struct spi_nor nor;
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u32 clk_rate;
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struct completion cmd_completion;
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};
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struct atmel_qspi_command {
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union {
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struct {
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u32 instruction:1;
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u32 address:3;
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u32 mode:1;
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u32 dummy:1;
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u32 data:1;
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u32 reserved:25;
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} bits;
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u32 word;
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} enable;
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u8 instruction;
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u8 mode;
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u8 num_mode_cycles;
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u8 num_dummy_cycles;
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u32 address;
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size_t buf_len;
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const void *tx_buf;
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void *rx_buf;
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};
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struct qspi_mode {
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u8 cmd_buswidth;
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u8 addr_buswidth;
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@ -407,363 +376,6 @@ static int atmel_qspi_setup(struct spi_device *spi)
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return 0;
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}
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static int atmel_qspi_run_transfer(struct atmel_qspi *aq,
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const struct atmel_qspi_command *cmd)
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{
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void __iomem *ahb_mem;
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/* Then fallback to a PIO transfer (memcpy() DOES NOT work!) */
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ahb_mem = aq->mem;
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if (cmd->enable.bits.address)
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ahb_mem += cmd->address;
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if (cmd->tx_buf)
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_memcpy_toio(ahb_mem, cmd->tx_buf, cmd->buf_len);
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else
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_memcpy_fromio(cmd->rx_buf, ahb_mem, cmd->buf_len);
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return 0;
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}
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#ifdef DEBUG
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static void atmel_qspi_debug_command(struct atmel_qspi *aq,
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const struct atmel_qspi_command *cmd,
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u32 ifr)
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{
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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size_t len = 0;
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int i;
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if (cmd->enable.bits.instruction)
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cmd_buf[len++] = cmd->instruction;
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for (i = cmd->enable.bits.address-1; i >= 0; --i)
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cmd_buf[len++] = (cmd->address >> (i << 3)) & 0xff;
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if (cmd->enable.bits.mode)
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cmd_buf[len++] = cmd->mode;
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if (cmd->enable.bits.dummy) {
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int num = cmd->num_dummy_cycles;
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switch (ifr & QSPI_IFR_WIDTH_MASK) {
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case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
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case QSPI_IFR_WIDTH_DUAL_OUTPUT:
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case QSPI_IFR_WIDTH_QUAD_OUTPUT:
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num >>= 3;
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break;
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case QSPI_IFR_WIDTH_DUAL_IO:
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case QSPI_IFR_WIDTH_DUAL_CMD:
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num >>= 2;
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break;
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case QSPI_IFR_WIDTH_QUAD_IO:
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case QSPI_IFR_WIDTH_QUAD_CMD:
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num >>= 1;
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break;
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default:
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return;
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}
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for (i = 0; i < num; ++i)
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cmd_buf[len++] = 0;
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}
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/* Dump the SPI command */
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print_hex_dump(KERN_DEBUG, "qspi cmd: ", DUMP_PREFIX_NONE,
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32, 1, cmd_buf, len, false);
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#ifdef VERBOSE_DEBUG
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/* If verbose debug is enabled, also dump the TX data */
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if (cmd->enable.bits.data && cmd->tx_buf)
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print_hex_dump(KERN_DEBUG, "qspi tx : ", DUMP_PREFIX_NONE,
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32, 1, cmd->tx_buf, cmd->buf_len, false);
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#endif
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}
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#else
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#define atmel_qspi_debug_command(aq, cmd, ifr)
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#endif
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static int atmel_qspi_run_command(struct atmel_qspi *aq,
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const struct atmel_qspi_command *cmd,
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u32 ifr_tfrtyp, enum spi_nor_protocol proto)
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{
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u32 iar, icr, ifr, sr;
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int err = 0;
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iar = 0;
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icr = 0;
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ifr = ifr_tfrtyp;
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/* Set the SPI protocol */
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switch (proto) {
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case SNOR_PROTO_1_1_1:
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ifr |= QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
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break;
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case SNOR_PROTO_1_1_2:
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ifr |= QSPI_IFR_WIDTH_DUAL_OUTPUT;
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break;
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case SNOR_PROTO_1_1_4:
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ifr |= QSPI_IFR_WIDTH_QUAD_OUTPUT;
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break;
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case SNOR_PROTO_1_2_2:
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ifr |= QSPI_IFR_WIDTH_DUAL_IO;
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break;
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case SNOR_PROTO_1_4_4:
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ifr |= QSPI_IFR_WIDTH_QUAD_IO;
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break;
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case SNOR_PROTO_2_2_2:
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ifr |= QSPI_IFR_WIDTH_DUAL_CMD;
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break;
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case SNOR_PROTO_4_4_4:
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ifr |= QSPI_IFR_WIDTH_QUAD_CMD;
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break;
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default:
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return -EINVAL;
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}
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/* Compute instruction parameters */
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if (cmd->enable.bits.instruction) {
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icr |= QSPI_ICR_INST(cmd->instruction);
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ifr |= QSPI_IFR_INSTEN;
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}
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/* Compute address parameters */
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switch (cmd->enable.bits.address) {
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case 4:
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ifr |= QSPI_IFR_ADDRL;
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/* fall through to the 24bit (3 byte) address case. */
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case 3:
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iar = (cmd->enable.bits.data) ? 0 : cmd->address;
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ifr |= QSPI_IFR_ADDREN;
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break;
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case 0:
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break;
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default:
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return -EINVAL;
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}
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/* Compute option parameters */
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if (cmd->enable.bits.mode && cmd->num_mode_cycles) {
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u32 mode_cycle_bits, mode_bits;
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icr |= QSPI_ICR_OPT(cmd->mode);
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ifr |= QSPI_IFR_OPTEN;
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switch (ifr & QSPI_IFR_WIDTH_MASK) {
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case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
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case QSPI_IFR_WIDTH_DUAL_OUTPUT:
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case QSPI_IFR_WIDTH_QUAD_OUTPUT:
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mode_cycle_bits = 1;
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break;
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case QSPI_IFR_WIDTH_DUAL_IO:
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case QSPI_IFR_WIDTH_DUAL_CMD:
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mode_cycle_bits = 2;
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break;
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case QSPI_IFR_WIDTH_QUAD_IO:
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case QSPI_IFR_WIDTH_QUAD_CMD:
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mode_cycle_bits = 4;
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break;
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default:
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return -EINVAL;
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}
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mode_bits = cmd->num_mode_cycles * mode_cycle_bits;
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switch (mode_bits) {
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case 1:
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ifr |= QSPI_IFR_OPTL_1BIT;
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break;
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case 2:
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ifr |= QSPI_IFR_OPTL_2BIT;
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break;
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case 4:
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ifr |= QSPI_IFR_OPTL_4BIT;
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break;
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case 8:
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ifr |= QSPI_IFR_OPTL_8BIT;
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break;
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default:
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return -EINVAL;
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}
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}
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/* Set number of dummy cycles */
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if (cmd->enable.bits.dummy)
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ifr |= QSPI_IFR_NBDUM(cmd->num_dummy_cycles);
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/* Set data enable */
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if (cmd->enable.bits.data) {
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ifr |= QSPI_IFR_DATAEN;
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/* Special case for Continuous Read Mode */
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if (!cmd->tx_buf && !cmd->rx_buf)
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ifr |= QSPI_IFR_CRM;
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}
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/* Clear pending interrupts */
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(void)qspi_readl(aq, QSPI_SR);
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/* Set QSPI Instruction Frame registers */
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atmel_qspi_debug_command(aq, cmd, ifr);
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qspi_writel(aq, QSPI_IAR, iar);
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qspi_writel(aq, QSPI_ICR, icr);
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qspi_writel(aq, QSPI_IFR, ifr);
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/* Skip to the final steps if there is no data */
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if (!cmd->enable.bits.data)
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goto no_data;
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/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
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(void)qspi_readl(aq, QSPI_IFR);
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/* Stop here for continuous read */
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if (!cmd->tx_buf && !cmd->rx_buf)
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return 0;
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/* Send/Receive data */
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err = atmel_qspi_run_transfer(aq, cmd);
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/* Release the chip-select */
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qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER);
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if (err)
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return err;
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#if defined(DEBUG) && defined(VERBOSE_DEBUG)
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/*
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* If verbose debug is enabled, also dump the RX data in addition to
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* the SPI command previously dumped by atmel_qspi_debug_command()
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*/
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if (cmd->rx_buf)
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print_hex_dump(KERN_DEBUG, "qspi rx : ", DUMP_PREFIX_NONE,
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32, 1, cmd->rx_buf, cmd->buf_len, false);
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#endif
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no_data:
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/* Poll INSTRuction End status */
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sr = qspi_readl(aq, QSPI_SR);
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if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
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return err;
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/* Wait for INSTRuction End interrupt */
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reinit_completion(&aq->cmd_completion);
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aq->pending = sr & QSPI_SR_CMD_COMPLETED;
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qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED);
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if (!wait_for_completion_timeout(&aq->cmd_completion,
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msecs_to_jiffies(1000)))
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err = -ETIMEDOUT;
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qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED);
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return err;
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}
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static int atmel_qspi_read_reg(struct spi_nor *nor, u8 opcode,
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u8 *buf, int len)
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{
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struct atmel_qspi *aq = nor->priv;
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struct atmel_qspi_command cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.enable.bits.instruction = 1;
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cmd.enable.bits.data = 1;
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cmd.instruction = opcode;
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cmd.rx_buf = buf;
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cmd.buf_len = len;
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return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ,
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nor->reg_proto);
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}
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static int atmel_qspi_write_reg(struct spi_nor *nor, u8 opcode,
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u8 *buf, int len)
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{
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struct atmel_qspi *aq = nor->priv;
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struct atmel_qspi_command cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.enable.bits.instruction = 1;
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cmd.enable.bits.data = (buf != NULL && len > 0);
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cmd.instruction = opcode;
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cmd.tx_buf = buf;
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cmd.buf_len = len;
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return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
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nor->reg_proto);
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}
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static ssize_t atmel_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
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const u_char *write_buf)
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{
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struct atmel_qspi *aq = nor->priv;
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struct atmel_qspi_command cmd;
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ssize_t ret;
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memset(&cmd, 0, sizeof(cmd));
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cmd.enable.bits.instruction = 1;
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cmd.enable.bits.address = nor->addr_width;
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cmd.enable.bits.data = 1;
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cmd.instruction = nor->program_opcode;
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cmd.address = (u32)to;
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cmd.tx_buf = write_buf;
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cmd.buf_len = len;
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ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM,
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nor->write_proto);
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return (ret < 0) ? ret : len;
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}
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static int atmel_qspi_erase(struct spi_nor *nor, loff_t offs)
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{
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struct atmel_qspi *aq = nor->priv;
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struct atmel_qspi_command cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.enable.bits.instruction = 1;
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cmd.enable.bits.address = nor->addr_width;
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cmd.instruction = nor->erase_opcode;
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cmd.address = (u32)offs;
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return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
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nor->reg_proto);
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}
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static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
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u_char *read_buf)
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{
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struct atmel_qspi *aq = nor->priv;
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struct atmel_qspi_command cmd;
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u8 num_mode_cycles, num_dummy_cycles;
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ssize_t ret;
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if (nor->read_dummy >= 2) {
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num_mode_cycles = 2;
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num_dummy_cycles = nor->read_dummy - 2;
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} else {
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num_mode_cycles = nor->read_dummy;
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num_dummy_cycles = 0;
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}
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memset(&cmd, 0, sizeof(cmd));
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cmd.enable.bits.instruction = 1;
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cmd.enable.bits.address = nor->addr_width;
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cmd.enable.bits.mode = (num_mode_cycles > 0);
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cmd.enable.bits.dummy = (num_dummy_cycles > 0);
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cmd.enable.bits.data = 1;
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cmd.instruction = nor->read_opcode;
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cmd.address = (u32)from;
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cmd.mode = 0xff; /* This value prevents from entering the 0-4-4 mode */
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cmd.num_mode_cycles = num_mode_cycles;
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cmd.num_dummy_cycles = num_dummy_cycles;
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cmd.rx_buf = read_buf;
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cmd.buf_len = len;
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ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ_MEM,
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nor->read_proto);
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return (ret < 0) ? ret : len;
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}
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static int atmel_qspi_init(struct atmel_qspi *aq)
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{
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/* Reset the QSPI controller */
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