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drm/amdgpu/gfx: switch to amdgpu_gfx_ras_late_init helper function
amdgpu_gfx_ras_late_init is used to init gfx specfic ras debugfs/sysfs node and gfx specific interrupt handler. It can be shared among gfx generations Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
a85eff14da
commit
6caeee7a70
3 changed files with 54 additions and 35 deletions
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@ -26,6 +26,7 @@
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include "amdgpu_rlc.h"
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#include "amdgpu_ras.h"
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/* delay 0.1 second to enable gfx off feature */
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#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100)
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@ -569,3 +570,51 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
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mutex_unlock(&adev->gfx.gfx_off_mutex);
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}
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int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
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void *ras_ih_info)
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{
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int r;
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struct ras_ih_if *ih_info = (struct ras_ih_if *)ras_ih_info;
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struct ras_fs_if fs_info = {
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.sysfs_name = "gfx_err_count",
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.debugfs_name = "gfx_err_inject",
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};
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if (!ih_info)
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return -EINVAL;
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if (!adev->gfx.ras_if) {
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adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
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if (!adev->gfx.ras_if)
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return -ENOMEM;
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adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
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adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->gfx.ras_if->sub_block_index = 0;
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strcpy(adev->gfx.ras_if->name, "gfx");
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}
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fs_info.head = ih_info->head = *adev->gfx.ras_if;
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r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
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&fs_info, ih_info);
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if (r)
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goto free;
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if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
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r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
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if (r)
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goto late_fini;
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} else {
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/* free gfx ras_if if ras is not supported */
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r = 0;
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goto free;
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}
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return 0;
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late_fini:
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amdgpu_ras_late_fini(adev, adev->gfx.ras_if, ih_info);
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free:
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kfree(adev->gfx.ras_if);
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adev->gfx.ras_if = NULL;
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return r;
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}
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@ -383,5 +383,6 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
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bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
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int pipe, int queue);
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void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
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int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev,
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void *ras_ih_info);
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#endif
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@ -4409,22 +4409,11 @@ static int gfx_v9_0_ecc_late_init(void *handle)
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struct ras_ih_if ih_info = {
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.cb = gfx_v9_0_process_ras_data_cb,
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};
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struct ras_fs_if fs_info = {
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.sysfs_name = "gfx_err_count",
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.debugfs_name = "gfx_err_inject",
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};
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int r;
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if (!adev->gfx.ras_if) {
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adev->gfx.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
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if (!adev->gfx.ras_if)
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return -ENOMEM;
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adev->gfx.ras_if->block = AMDGPU_RAS_BLOCK__GFX;
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adev->gfx.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
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adev->gfx.ras_if->sub_block_index = 0;
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strcpy(adev->gfx.ras_if->name, "gfx");
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}
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fs_info.head = ih_info.head = *adev->gfx.ras_if;
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r = amdgpu_gfx_ras_late_init(adev, &ih_info);
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if (r)
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return r;
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r = gfx_v9_0_do_edc_gds_workarounds(adev);
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if (r)
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@ -4435,27 +4424,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
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if (r)
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return r;
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r = amdgpu_ras_late_init(adev, adev->gfx.ras_if,
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&fs_info, &ih_info);
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if (r)
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goto free;
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if (amdgpu_ras_is_supported(adev, adev->gfx.ras_if->block)) {
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r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
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if (r)
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goto late_fini;
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} else {
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r = 0;
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goto free;
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}
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return 0;
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late_fini:
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amdgpu_ras_late_fini(adev, adev->gfx.ras_if, &ih_info);
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free:
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kfree(adev->gfx.ras_if);
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adev->gfx.ras_if = NULL;
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return r;
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}
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static int gfx_v9_0_late_init(void *handle)
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