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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Ux500 core changes for the v6.2 kernel cycle:
- Spelling error. - A non-urgent fix to not access IOmem for feeding entropy directly, instead copy and use. - Clean out an old register file. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmNqwPsACgkQQRCzN7AZ XXNgsw//SDGUnbGYw6pjT5X1cbhXdmZvxys/wgyn6vrYeFeD803N62OUk1NoVQyJ nBpGz0ZJ6n8wBnQMIR7jPkeVaVC3siWAxvYWchqxGUXkUVY62x5GlfKUTIL/A8PD mzEfPF8EB8ji/EMIYemcIcADPz4uaxwEuSl5eeUxWkclpyD+hjtHxGUWO4AD6jwS Z5+1lyJ3gDGhLLFBNCtZhELZ7mdfgONJuskwp/dGVSBhj5AZbizLgH0I1mCUdDQE d2Zv2rus1QUTUTvb4wanZgkx1hLv2Kd+cQeRQVnlZUdH2oNUZf5RRCSh36woo8VM sR3vsgMjoeVBvM+zWz8JfWW1Q6i6NcBxNnhBnzjoaZATHz2mUhpDQTGGn5WGnhNE C3Y4MMVuC21632MJxQTempdz3w1AVej63IwSGJJ2gIX9zTpSLApLyRk+L41kty4T Wi0ar2Ou6lW45lUzLv2FKShbYte85hRxHPmbWTZcHST008SS6XUwjIKx6frT/fOa WnJ+JslV/4na3Fme9Q2admeAUHJn3bpt6jsXM/u3tJzo8m3Kta/b888pmmZsS0lK mz/aBJhsUhode/Enwnp5x+xFiFwodz9UjDF4+zWatw/I6C470/L7aMESAA2A6Vtr Brh3mNJa/gO/PMycFqXkHlqm3irgxcPNhmAUQ/ROordJFrlli6I= =0Cgk -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmNyWNYACgkQmmx57+YA GNkPIRAAnU2oWm89f388bln9HIYG41UUkJIh5+w/w19yh9sxiP1hOJMYjEvrSnbG A5kmYhgC9bIDIOjReWljGu1e2CtzyC2cVdtpamkYKdo6u+B6bo/KXAF5wcG2olAm 0fV/cSkGYGHWJq2Ukmkj2tQ6u8bqZxnn72uq6zasFRAH/0l8GYr21X5Jv+xovSKB dsTTLhxcxanU5Pw84gvYhdLteiz+KVsOiOS++CRadNGGXNyHMikA16Pdzb7e3SP9 KVzgcJIiMH+ynAh7EOyEjCWH9/EDmGRUA9poWTImT2otN0SkXCkGpY5GTI/UoDte vsXToGR6Pp8hGPSS9L5ZgKK2+tMeNh110WNswB1KCBQqtL2TFvO94vJai90XRsS5 7/Ejn62MkArHcFFe7G8tPO9Z/DweWyqDWUzt3OqK/0O4NBW4bOYMQHiYvEnLjviv HaqPinMKg6TsDv9DaLIDrdd1uOssH7XBWspruo7Me9LoPZn3VJ8RsNROPrATGWZI mNm8AuGTh5oAYQIjmxZ7yn8xo52wShN0dAb5CCkOV8xli/MOusGFQT/Ylofx1qID NcLlUK1E4sbt8bAn/jRRNTU2CCw+uRbw5znwoBgkS6key4bKXdIohPPeJijPFbh5 oPh+dsjxHhYymXG7fR5UXwAEErHhBmFTHBBhI4S4Y8GBeFYikHE= =9Qze -----END PGP SIGNATURE----- Merge tag 'ux500-soc-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/soc Ux500 core changes for the v6.2 kernel cycle: - Spelling error. - A non-urgent fix to not access IOmem for feeding entropy directly, instead copy and use. - Clean out an old register file. * tag 'ux500-soc-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: ux500: Drop unused register file ARM: ux500: do not directly dereference __iomem arm/mach-ux500: fix repeated words in comments Link: https://lore.kernel.org/r/CACRpkdaPDbJKUzZHsS2POVUQEjYi+6bjU6cvbg4ox=SKPXG2ng@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
6cb1253c6d
5 changed files with 5 additions and 207 deletions
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@ -26,7 +26,6 @@
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#include <asm/mach/map.h>
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#include <asm/mach/arch.h>
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#include "db8500-regs.h"
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#include "pm_domains.h"
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static int __init ux500_l2x0_unlock(void)
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@ -1,195 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) ST-Ericsson SA 2010
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*/
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#ifndef __MACH_DB8500_REGS_H
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#define __MACH_DB8500_REGS_H
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/* Base address and bank offsets for ESRAM */
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#define U8500_ESRAM_BASE 0x40000000
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#define U8500_ESRAM_BANK_SIZE 0x00020000
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#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE
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#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
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#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
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/*
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* on V1 DMA uses 4KB for logical parameters position is right after the 64KB
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* reserved for security
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*/
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#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
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#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
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/* This address fulfills the 256k alignment requirement of the lcla base */
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#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
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#define U8500_PER3_BASE 0x80000000
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#define U8500_STM_BASE 0x80100000
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#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
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#define U8500_PER2_BASE 0x80110000
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#define U8500_PER1_BASE 0x80120000
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#define U8500_B2R2_BASE 0x80130000
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#define U8500_HSEM_BASE 0x80140000
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#define U8500_PER4_BASE 0x80150000
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#define U8500_TPIU_BASE 0x80190000
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#define U8500_ICN_BASE 0x81000000
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#define U8500_BOOT_ROM_BASE 0x90000000
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/* ASIC ID is at 0xbf4 offset within this region */
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#define U8500_ASIC_ID_BASE 0x9001D000
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#define U8500_PER6_BASE 0xa03c0000
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#define U8500_PER7_BASE 0xa03d0000
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#define U8500_PER5_BASE 0xa03e0000
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#define U8500_SVA_BASE 0xa0100000
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#define U8500_SIA_BASE 0xa0200000
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#define U8500_SGA_BASE 0xa0300000
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#define U8500_MCDE_BASE 0xa0350000
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#define U8500_DMA_BASE 0x801C0000 /* v1 */
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#define U8500_SBAG_BASE 0xa0390000
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#define U8500_SCU_BASE 0xa0410000
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#define U8500_GIC_CPU_BASE 0xa0410100
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#define U8500_TWD_BASE 0xa0410600
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#define U8500_GIC_DIST_BASE 0xa0411000
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#define U8500_L2CC_BASE 0xa0412000
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#define U8500_MODEM_I2C 0xb7e02000
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#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
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#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
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#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
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#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
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#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
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#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
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/* per6 base addresses */
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#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
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#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000)
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#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000)
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#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000)
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#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100)
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#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
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#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
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#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
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#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000)
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#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000)
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#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
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/* per5 base addresses */
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#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
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#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
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/* per4 base addresses */
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#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
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#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
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#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
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#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
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#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
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#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
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#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
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#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
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#define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000)
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#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
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#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
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#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
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#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
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/* per3 base addresses */
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#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
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#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
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#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
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#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
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#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
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#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
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#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
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#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
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#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
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/* per2 base addresses */
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#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
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#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
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#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
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#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
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#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
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#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
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#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
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#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
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#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
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#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
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#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
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#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
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/* per1 base addresses */
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#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
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#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
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#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
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#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000)
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#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
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#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
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#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
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#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
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#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
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#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
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#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
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#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
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#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
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#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
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#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
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#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
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#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
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#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
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#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
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#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
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#define U8500_MCDE_SIZE 0x1000
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#define U8500_DSI_LINK_SIZE 0x1000
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#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE)
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#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
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#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
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#define U8500_DSI_LINK_COUNT 0x3
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/* Modem and APE physical addresses */
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#define U8500_MODEM_BASE 0xe000000
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#define U8500_APE_BASE 0x6000000
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/* SoC identification number information */
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#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0)
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/* Offsets to specific addresses in some IP blocks for DMA */
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#define MSP_TX_RX_REG_OFFSET 0
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#define CRYP1_RX_REG_OFFSET 0x10
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#define CRYP1_TX_REG_OFFSET 0x8
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#define HASH1_TX_REG_OFFSET 0x4
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/*
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* Macros to get at IO space when running virtually
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* We dont map all the peripherals, let ioremap do
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* this for us. We map only very basic peripherals here.
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*/
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#define U8500_IO_VIRTUAL 0xf0000000
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#define U8500_IO_PHYSICAL 0xa0000000
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/* This is where we map in the ROM to check ASIC IDs */
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#define UX500_VIRT_ROM IOMEM(0xf0000000)
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/* This macro is used in assembly, so no cast */
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#define IO_ADDRESS(x) \
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(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
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/* typesafe io address */
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#define __io_address(n) IOMEM(IO_ADDRESS(n))
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/* Used by some plat-nomadik code */
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#define io_p2v(n) __io_address(n)
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#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
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#endif
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@ -20,8 +20,6 @@
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "db8500-regs.h"
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/* Magic triggers in backup RAM */
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#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
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#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
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@ -16,8 +16,6 @@
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "db8500-regs.h"
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/* ARM WFI Standby signal register */
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#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
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#define PRCM_ARM_WFI_STANDBY_WFI0 0x08
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@ -124,7 +122,7 @@ bool prcmu_pending_irq(void)
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}
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/*
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* This function checks if the specified cpu is in in WFI. It's usage
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* This function checks if the specified cpu is in WFI. It's usage
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* makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
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* function. Of course passing smp_processor_id() to this function will
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* always return false...
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@ -167,20 +167,18 @@ ATTRIBUTE_GROUPS(ux500_soc);
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static const char *db8500_read_soc_id(struct device_node *backupram)
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{
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void __iomem *base;
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void __iomem *uid;
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const char *retstr;
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u32 uid[5];
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base = of_iomap(backupram, 0);
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if (!base)
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return NULL;
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uid = base + 0x1fc0;
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memcpy_fromio(uid, base + 0x1fc0, sizeof(uid));
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/* Throw these device-specific numbers into the entropy pool */
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add_device_randomness(uid, 0x14);
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add_device_randomness(uid, sizeof(uid));
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retstr = kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
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readl((u32 *)uid+0),
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readl((u32 *)uid+1), readl((u32 *)uid+2),
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readl((u32 *)uid+3), readl((u32 *)uid+4));
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uid[0], uid[1], uid[2], uid[3], uid[4]);
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iounmap(base);
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return retstr;
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}
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