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PCI: designware: Wait for link to come up with consistent style
All the DesignWare-based host drivers loop waiting for the link to come up, but they do it several ways that are needlessly different. Wait for the link to come up in a consistent style across all the DesignWare drivers. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
This commit is contained in:
parent
1d3f9bac71
commit
6cbb247e85
6 changed files with 51 additions and 66 deletions
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@ -93,9 +93,9 @@ static int dra7xx_pcie_link_up(struct pcie_port *pp)
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static int dra7xx_pcie_establish_link(struct pcie_port *pp)
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{
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u32 reg;
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unsigned int retries = 1000;
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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u32 reg;
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unsigned int retries;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "link is already up\n");
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@ -106,18 +106,14 @@ static int dra7xx_pcie_establish_link(struct pcie_port *pp)
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reg |= LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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while (retries--) {
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for (retries = 0; retries < 1000; retries++) {
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if (dw_pcie_link_up(pp))
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break;
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return 0;
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usleep_range(10, 20);
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}
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if (retries == 0) {
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dev_err(pp->dev, "link is not up\n");
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return -ETIMEDOUT;
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}
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return 0;
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dev_err(pp->dev, "link is not up\n");
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return -EINVAL;
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}
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static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
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@ -316,9 +316,9 @@ static void exynos_pcie_assert_reset(struct pcie_port *pp)
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static int exynos_pcie_establish_link(struct pcie_port *pp)
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{
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u32 val;
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int count = 0;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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u32 val;
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unsigned int retries;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "Link already up\n");
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@ -357,27 +357,23 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
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PCIE_APP_LTSSM_ENABLE);
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/* check if the link is up or not */
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while (!dw_pcie_link_up(pp)) {
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mdelay(100);
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count++;
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if (count == 10) {
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while (exynos_phy_readl(exynos_pcie,
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PCIE_PHY_PLL_LOCKED) == 0) {
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val = exynos_blk_readl(exynos_pcie,
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PCIE_PHY_PLL_LOCKED);
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dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
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}
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/* power off phy */
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exynos_pcie_power_off_phy(pp);
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dev_err(pp->dev, "PCIe Link Fail\n");
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return -EINVAL;
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for (retries = 0; retries < 10; retries++) {
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if (dw_pcie_link_up(pp)) {
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dev_info(pp->dev, "Link up\n");
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return 0;
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}
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mdelay(100);
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}
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dev_info(pp->dev, "Link up\n");
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while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
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val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
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dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
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}
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/* power off phy */
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exynos_pcie_power_off_phy(pp);
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return 0;
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dev_err(pp->dev, "PCIe Link Fail\n");
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return -EINVAL;
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}
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static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
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@ -335,21 +335,19 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
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static int imx6_pcie_wait_for_link(struct pcie_port *pp)
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{
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int count = 200;
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unsigned int retries;
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while (!dw_pcie_link_up(pp)) {
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for (retries = 0; retries < 200; retries++) {
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if (dw_pcie_link_up(pp))
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return 0;
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usleep_range(100, 1000);
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if (--count)
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continue;
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dev_err(pp->dev, "phy link never came up\n");
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dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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return -EINVAL;
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}
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return 0;
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dev_err(pp->dev, "phy link never came up\n");
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dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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return -EINVAL;
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}
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static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
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@ -88,7 +88,7 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
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static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
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{
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struct pcie_port *pp = &ks_pcie->pp;
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int count = 200;
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unsigned int retries;
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dw_pcie_setup_rc(pp);
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@ -99,17 +99,15 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
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ks_dw_pcie_initiate_link_train(ks_pcie);
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/* check if the link is up or not */
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while (!dw_pcie_link_up(pp)) {
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for (retries = 0; retries < 200; retries++) {
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if (dw_pcie_link_up(pp))
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return 0;
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usleep_range(100, 1000);
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if (--count) {
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ks_dw_pcie_initiate_link_train(ks_pcie);
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continue;
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}
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dev_err(pp->dev, "phy link never came up\n");
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return -EINVAL;
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ks_dw_pcie_initiate_link_train(ks_pcie);
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}
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return 0;
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dev_err(pp->dev, "phy link never came up\n");
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return -EINVAL;
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}
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static void ks_pcie_msi_irq_handler(unsigned int irq, struct irq_desc *desc)
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@ -64,18 +64,16 @@ static int ls_pcie_link_up(struct pcie_port *pp)
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static int ls_pcie_establish_link(struct pcie_port *pp)
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{
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int count = 0;
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unsigned int retries;
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while (!dw_pcie_link_up(pp)) {
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for (retries = 0; retries < 200; retries++) {
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if (dw_pcie_link_up(pp))
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return 0;
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usleep_range(100, 1000);
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count++;
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if (count >= 200) {
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dev_err(pp->dev, "phy link never came up\n");
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return -EINVAL;
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}
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}
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return 0;
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dev_err(pp->dev, "phy link never came up\n");
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return -EINVAL;
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}
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static void ls_pcie_host_init(struct pcie_port *pp)
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@ -146,10 +146,10 @@ struct pcie_app_reg {
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static int spear13xx_pcie_establish_link(struct pcie_port *pp)
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{
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u32 val;
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int count = 0;
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struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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unsigned int retries;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "link already up\n");
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@ -201,17 +201,16 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp)
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&app_reg->app_ctrl_0);
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/* check if the link is up or not */
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while (!dw_pcie_link_up(pp)) {
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mdelay(100);
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count++;
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if (count == 10) {
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dev_err(pp->dev, "link Fail\n");
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return -EINVAL;
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for (retries = 0; retries < 10; retries++) {
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if (dw_pcie_link_up(pp)) {
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dev_info(pp->dev, "link up\n");
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return 0;
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}
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mdelay(100);
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}
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dev_info(pp->dev, "link up\n");
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return 0;
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dev_err(pp->dev, "link Fail\n");
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return -EINVAL;
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}
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static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
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