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drm/i915: Kill INTEL_SUBPLATFORM_AML
All AML parts are either KBL ULX or CFL ULX so there is no point in keeping INTEL_SUBPLATFORM_AML around. As these are the only CFL ULX parts (normal CFL didn't have Y SKUs) so we'll just replace IS_AML_ULX with IS_CFL_ULX (it was already paired with IS_KBL_ULX which accounts for the other half of the AML parts). Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190605162946.19223-2-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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4 changed files with 7 additions and 13 deletions
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@ -2223,9 +2223,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
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#define IS_KBL_ULX(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
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#define IS_AML_ULX(dev_priv) \
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(IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_AML) || \
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IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_AML))
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#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
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@ -2238,6 +2235,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_CFL_ULT(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
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#define IS_CFL_ULX(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
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#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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@ -615,7 +615,7 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
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static const struct ddi_buf_trans *
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kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
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{
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if (IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
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if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv)) {
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*n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
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return kbl_y_ddi_translations_dp;
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} else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
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@ -631,7 +631,8 @@ static const struct ddi_buf_trans *
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skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
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{
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if (dev_priv->vbt.edp.low_vswing) {
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if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
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if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
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IS_CFL_ULX(dev_priv)) {
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*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
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return skl_y_ddi_translations_edp;
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} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
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@ -653,7 +654,8 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
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static const struct ddi_buf_trans *
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skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
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{
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if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || IS_AML_ULX(dev_priv)) {
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if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) ||
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IS_CFL_ULX(dev_priv)) {
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*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
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return skl_y_ddi_translations_hdmi;
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} else {
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@ -787,9 +787,6 @@ static const u16 subplatform_ulx_ids[] = {
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INTEL_SKL_ULX_GT2_IDS(0),
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INTEL_KBL_ULX_GT1_IDS(0),
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INTEL_KBL_ULX_GT2_IDS(0),
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};
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static const u16 subplatform_aml_ids[] = {
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INTEL_AML_KBL_GT2_IDS(0),
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INTEL_AML_CFL_GT2_IDS(0),
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};
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@ -832,9 +829,6 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
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/* ULX machines are also considered ULT. */
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mask |= BIT(INTEL_SUBPLATFORM_ULT);
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}
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} else if (find_devid(devid, subplatform_aml_ids,
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ARRAY_SIZE(subplatform_aml_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_AML);
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} else if (find_devid(devid, subplatform_portf_ids,
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ARRAY_SIZE(subplatform_portf_ids))) {
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mask = BIT(INTEL_SUBPLATFORM_PORTF);
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@ -91,7 +91,6 @@ enum intel_platform {
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/* HSW/BDW/SKL/KBL/CFL */
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#define INTEL_SUBPLATFORM_ULT (0)
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#define INTEL_SUBPLATFORM_ULX (1)
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#define INTEL_SUBPLATFORM_AML (2)
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/* CNL/ICL */
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#define INTEL_SUBPLATFORM_PORTF (0)
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