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habanalabs/gaudi2: avoid reconfiguring the same PB registers
It appears that, within the sync manager security configuration, we reconfigure PB registers over and over without any need to do that. Signed-off-by: Koby Elbaz <kelbaz@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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4083697a36
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6cfb00139d
3 changed files with 1224 additions and 16 deletions
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@ -1666,6 +1666,10 @@ static const u32 gaudi2_pb_dcr0_sm_glbl[] = {
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mmDCORE0_SYNC_MNGR_GLBL_BASE,
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};
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static const u32 gaudi2_pb_dcr1_sm_glbl[] = {
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mmDCORE1_SYNC_MNGR_GLBL_BASE,
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};
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static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {
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{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
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{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
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@ -1678,14 +1682,14 @@ static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {
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};
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static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = {
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{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
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{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
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{mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
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{mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},
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{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
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{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
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{mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},
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{mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
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{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
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{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
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{mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
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{mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63},
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{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
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{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
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{mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63},
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{mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
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};
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static const u32 gaudi2_pb_arc_sched[] = {
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@ -3358,14 +3362,6 @@ static int gaudi2_init_protection_bits(struct hl_device *hdev)
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/* Sync Manager GLBL */
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/* Unsecure all CQ registers */
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rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES, DCORE_OFFSET,
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HL_PB_SINGLE_INSTANCE, HL_PB_NA,
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gaudi2_pb_dcr0_sm_glbl,
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ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),
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gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,
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ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));
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/* Secure Dcore0 CQ0 registers */
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rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
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HL_PB_SINGLE_INSTANCE, HL_PB_NA,
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@ -3374,6 +3370,14 @@ static int gaudi2_init_protection_bits(struct hl_device *hdev)
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gaudi2_pb_dcr0_sm_glbl_unsecured_regs,
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ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs));
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/* Unsecure all other CQ registers */
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rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,
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HL_PB_SINGLE_INSTANCE, HL_PB_NA,
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gaudi2_pb_dcr1_sm_glbl,
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ARRAY_SIZE(gaudi2_pb_dcr1_sm_glbl),
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gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,
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ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));
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/* PSOC.
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* Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
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* protected by privileged RR.
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File diff suppressed because it is too large
Load diff
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@ -31,6 +31,7 @@
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#include "dcore0_sync_mngr_objs_regs.h"
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#include "dcore0_sync_mngr_glbl_regs.h"
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#include "dcore0_sync_mngr_mstr_if_axuser_regs.h"
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#include "dcore1_sync_mngr_glbl_regs.h"
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#include "pdma0_qm_arc_aux_regs.h"
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#include "pdma0_core_ctx_regs.h"
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#include "pdma0_core_regs.h"
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