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e1000e: fix Rapid Start Technology support for i217
The definition of I217_PROXY_CTRL must use the BM_PHY_REG() macro instead of the PHY_REG() macro for PHY page 800 register 70 since it is for a PHY register greater than the maximum allowed by the latter macro, and fix a typo setting the I217_MEMPWR register in e1000_suspend_workarounds_ich8lan. Also for clarity, rename a few defines as bit definitions instead of masks. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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parent
281a8f2462
commit
6d7407bfba
1 changed files with 9 additions and 9 deletions
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@ -165,14 +165,14 @@
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#define I217_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */
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#define I217_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */
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/* Intel Rapid Start Technology Support */
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/* Intel Rapid Start Technology Support */
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#define I217_PROXY_CTRL PHY_REG(BM_WUC_PAGE, 70)
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#define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
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#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
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#define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
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#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
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#define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
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#define I217_SxCTRL_MASK 0x1000
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#define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
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#define I217_CGFREG PHY_REG(772, 29)
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#define I217_CGFREG PHY_REG(772, 29)
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#define I217_CGFREG_MASK 0x0002
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#define I217_CGFREG_ENABLE_MTA_RESET 0x0002
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#define I217_MEMPWR PHY_REG(772, 26)
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#define I217_MEMPWR PHY_REG(772, 26)
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#define I217_MEMPWR_MASK 0x0010
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#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
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/* Strapping Option Register - RO */
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/* Strapping Option Register - RO */
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#define E1000_STRAP 0x0000C
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#define E1000_STRAP 0x0000C
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@ -4089,12 +4089,12 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
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* power good.
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* power good.
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*/
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*/
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e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
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e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
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phy_reg |= I217_SxCTRL_MASK;
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phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
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e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
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e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
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/* Disable the SMB release on LCD reset. */
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/* Disable the SMB release on LCD reset. */
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e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
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e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
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phy_reg &= ~I217_MEMPWR;
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phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
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e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
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e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
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}
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}
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@ -4103,7 +4103,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
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* Support
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* Support
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*/
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*/
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e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
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e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
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phy_reg |= I217_CGFREG_MASK;
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phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
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e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
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e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
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release:
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release:
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@ -4176,7 +4176,7 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
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ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
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ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
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if (ret_val)
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if (ret_val)
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goto release;
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goto release;
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phy_reg |= I217_MEMPWR_MASK;
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phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
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e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
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e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
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/* Disable Proxy */
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/* Disable Proxy */
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@ -4186,7 +4186,7 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
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ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
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ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
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if (ret_val)
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if (ret_val)
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goto release;
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goto release;
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phy_reg &= ~I217_CGFREG_MASK;
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phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
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e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
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e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
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release:
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release:
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if (ret_val)
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if (ret_val)
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