mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-29 23:53:32 +00:00
drm/i915/gvt: Move common vGPU workload creation into scheduler.c
Move common vGPU workload creation functions into scheduler.c since they are not specific to execlist emulation. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
This commit is contained in:
Zhi Wang
Zhenyu Wang
parent
d8235b5e55
commit
6d76303553
3 changed files with 184 additions and 173 deletions
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@ -438,179 +438,29 @@ static int complete_execlist_workload(struct intel_vgpu_workload *workload)
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return ret;
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}
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#define RING_CTX_OFF(x) \
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offsetof(struct execlist_ring_context, x)
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static void read_guest_pdps(struct intel_vgpu *vgpu,
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u64 ring_context_gpa, u32 pdp[8])
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{
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u64 gpa;
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int i;
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gpa = ring_context_gpa + RING_CTX_OFF(pdp3_UDW.val);
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for (i = 0; i < 8; i++)
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intel_gvt_hypervisor_read_gpa(vgpu,
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gpa + i * 8, &pdp[7 - i], 4);
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}
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static int prepare_mm(struct intel_vgpu_workload *workload)
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{
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struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
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struct intel_vgpu_mm *mm;
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struct intel_vgpu *vgpu = workload->vgpu;
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int page_table_level;
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u32 pdp[8];
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if (desc->addressing_mode == 1) { /* legacy 32-bit */
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page_table_level = 3;
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} else if (desc->addressing_mode == 3) { /* legacy 64 bit */
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page_table_level = 4;
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} else {
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gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
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return -EINVAL;
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}
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read_guest_pdps(workload->vgpu, workload->ring_context_gpa, pdp);
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mm = intel_vgpu_find_ppgtt_mm(workload->vgpu, page_table_level, pdp);
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if (mm) {
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intel_gvt_mm_reference(mm);
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} else {
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mm = intel_vgpu_create_mm(workload->vgpu, INTEL_GVT_MM_PPGTT,
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pdp, page_table_level, 0);
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if (IS_ERR(mm)) {
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gvt_vgpu_err("fail to create mm object.\n");
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return PTR_ERR(mm);
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}
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}
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workload->shadow_mm = mm;
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return 0;
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}
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#define get_last_workload(q) \
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(list_empty(q) ? NULL : container_of(q->prev, \
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struct intel_vgpu_workload, list))
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static int submit_context(struct intel_vgpu *vgpu, int ring_id,
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struct execlist_ctx_descriptor_format *desc,
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bool emulate_schedule_in)
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{
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struct intel_vgpu_submission *s = &vgpu->submission;
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struct list_head *q = workload_q_head(vgpu, ring_id);
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struct intel_vgpu_workload *last_workload = get_last_workload(q);
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struct intel_vgpu_workload *workload = NULL;
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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u64 ring_context_gpa;
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u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
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int ret;
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ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
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(u32)((desc->lrca + 1) << GTT_PAGE_SHIFT));
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if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
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gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
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return -EINVAL;
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}
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(ring_header.val), &head, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(ring_tail.val), &tail, 4);
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head &= RB_HEAD_OFF_MASK;
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tail &= RB_TAIL_OFF_MASK;
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if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
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gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
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gvt_dbg_el("ctx head %x real head %lx\n", head,
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last_workload->rb_tail);
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/*
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* cannot use guest context head pointer here,
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* as it might not be updated at this time
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*/
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head = last_workload->rb_tail;
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}
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gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
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/* record some ring buffer register values for scan and shadow */
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(rb_start.val), &start, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
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workload = intel_vgpu_create_workload(vgpu);
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workload = intel_vgpu_create_workload(vgpu, ring_id, desc);
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if (IS_ERR(workload))
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return PTR_ERR(workload);
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workload->ring_id = ring_id;
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workload->ctx_desc = *desc;
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workload->ring_context_gpa = ring_context_gpa;
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workload->rb_head = head;
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workload->rb_tail = tail;
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workload->rb_start = start;
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workload->rb_ctl = ctl;
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workload->prepare = prepare_execlist_workload;
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workload->complete = complete_execlist_workload;
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workload->emulate_schedule_in = emulate_schedule_in;
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if (ring_id == RCS) {
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
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workload->wa_ctx.indirect_ctx.guest_gma =
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indirect_ctx & INDIRECT_CTX_ADDR_MASK;
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workload->wa_ctx.indirect_ctx.size =
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(indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
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CACHELINE_BYTES;
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workload->wa_ctx.per_ctx.guest_gma =
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per_ctx & PER_CTX_ADDR_MASK;
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workload->wa_ctx.per_ctx.valid = per_ctx & 1;
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}
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if (emulate_schedule_in)
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workload->elsp_dwords = s->execlist[ring_id].elsp_dwords;
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gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
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workload, ring_id, head, tail, start, ctl);
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gvt_dbg_el("workload %p emulate schedule_in %d\n", workload,
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emulate_schedule_in);
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ret = prepare_mm(workload);
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if (ret) {
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kmem_cache_free(s->workloads, workload);
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return ret;
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}
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/* Only scan and shadow the first workload in the queue
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* as there is only one pre-allocated buf-obj for shadow.
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*/
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if (list_empty(workload_q_head(vgpu, ring_id))) {
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev_priv->drm.struct_mutex);
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ret = intel_gvt_scan_and_shadow_workload(workload);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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intel_runtime_pm_put(dev_priv);
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}
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if (ret == 0)
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queue_workload(workload);
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else {
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intel_vgpu_destroy_workload(workload);
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if (vgpu_is_vm_unhealthy(ret)) {
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intel_vgpu_clean_execlist(vgpu);
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enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
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}
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}
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return ret;
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queue_workload(workload);
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return 0;
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}
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int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id)
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@ -792,13 +792,8 @@ static int workload_thread(void *priv)
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FORCEWAKE_ALL);
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intel_runtime_pm_put(gvt->dev_priv);
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if (ret && (vgpu_is_vm_unhealthy(ret))) {
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mutex_lock(&gvt->lock);
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intel_vgpu_clean_execlist(vgpu);
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mutex_unlock(&gvt->lock);
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if (ret && (vgpu_is_vm_unhealthy(ret)))
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enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
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}
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}
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return 0;
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}
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@ -957,19 +952,8 @@ void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
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kmem_cache_free(s->workloads, workload);
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}
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/**
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* intel_vgpu_create_workload - create a vGPU workload
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* @vgpu: a vGPU
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*
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* This function is called when creating a vGPU workload.
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*
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* Returns:
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* struct intel_vgpu_workload * on success, negative error code in
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* pointer if failed.
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*
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*/
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struct intel_vgpu_workload *
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intel_vgpu_create_workload(struct intel_vgpu *vgpu)
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static struct intel_vgpu_workload *
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alloc_workload(struct intel_vgpu *vgpu)
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{
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struct intel_vgpu_submission *s = &vgpu->submission;
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struct intel_vgpu_workload *workload;
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@ -990,3 +974,179 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu)
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return workload;
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}
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#define RING_CTX_OFF(x) \
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offsetof(struct execlist_ring_context, x)
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static void read_guest_pdps(struct intel_vgpu *vgpu,
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u64 ring_context_gpa, u32 pdp[8])
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{
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u64 gpa;
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int i;
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gpa = ring_context_gpa + RING_CTX_OFF(pdp3_UDW.val);
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for (i = 0; i < 8; i++)
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intel_gvt_hypervisor_read_gpa(vgpu,
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gpa + i * 8, &pdp[7 - i], 4);
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}
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static int prepare_mm(struct intel_vgpu_workload *workload)
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{
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struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
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struct intel_vgpu_mm *mm;
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struct intel_vgpu *vgpu = workload->vgpu;
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int page_table_level;
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u32 pdp[8];
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if (desc->addressing_mode == 1) { /* legacy 32-bit */
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page_table_level = 3;
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} else if (desc->addressing_mode == 3) { /* legacy 64 bit */
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page_table_level = 4;
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} else {
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gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
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return -EINVAL;
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}
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read_guest_pdps(workload->vgpu, workload->ring_context_gpa, pdp);
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mm = intel_vgpu_find_ppgtt_mm(workload->vgpu, page_table_level, pdp);
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if (mm) {
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intel_gvt_mm_reference(mm);
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} else {
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mm = intel_vgpu_create_mm(workload->vgpu, INTEL_GVT_MM_PPGTT,
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pdp, page_table_level, 0);
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if (IS_ERR(mm)) {
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gvt_vgpu_err("fail to create mm object.\n");
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return PTR_ERR(mm);
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}
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}
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workload->shadow_mm = mm;
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return 0;
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}
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#define same_context(a, b) (((a)->context_id == (b)->context_id) && \
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((a)->lrca == (b)->lrca))
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#define get_last_workload(q) \
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(list_empty(q) ? NULL : container_of(q->prev, \
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struct intel_vgpu_workload, list))
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/**
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* intel_vgpu_create_workload - create a vGPU workload
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* @vgpu: a vGPU
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* @desc: a guest context descriptor
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*
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* This function is called when creating a vGPU workload.
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*
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* Returns:
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* struct intel_vgpu_workload * on success, negative error code in
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* pointer if failed.
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*
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*/
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struct intel_vgpu_workload *
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intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
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struct execlist_ctx_descriptor_format *desc)
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{
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struct intel_vgpu_submission *s = &vgpu->submission;
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struct list_head *q = workload_q_head(vgpu, ring_id);
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struct intel_vgpu_workload *last_workload = get_last_workload(q);
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struct intel_vgpu_workload *workload = NULL;
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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u64 ring_context_gpa;
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u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
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int ret;
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ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
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(u32)((desc->lrca + 1) << GTT_PAGE_SHIFT));
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if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
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gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
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return ERR_PTR(-EINVAL);
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}
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(ring_header.val), &head, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(ring_tail.val), &tail, 4);
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head &= RB_HEAD_OFF_MASK;
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tail &= RB_TAIL_OFF_MASK;
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if (last_workload && same_context(&last_workload->ctx_desc, desc)) {
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gvt_dbg_el("ring id %d cur workload == last\n", ring_id);
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gvt_dbg_el("ctx head %x real head %lx\n", head,
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last_workload->rb_tail);
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/*
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* cannot use guest context head pointer here,
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* as it might not be updated at this time
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*/
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head = last_workload->rb_tail;
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}
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gvt_dbg_el("ring id %d begin a new workload\n", ring_id);
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/* record some ring buffer register values for scan and shadow */
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(rb_start.val), &start, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
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workload = alloc_workload(vgpu);
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if (IS_ERR(workload))
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return workload;
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workload->ring_id = ring_id;
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workload->ctx_desc = *desc;
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workload->ring_context_gpa = ring_context_gpa;
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workload->rb_head = head;
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workload->rb_tail = tail;
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workload->rb_start = start;
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workload->rb_ctl = ctl;
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if (ring_id == RCS) {
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
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intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
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RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
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workload->wa_ctx.indirect_ctx.guest_gma =
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indirect_ctx & INDIRECT_CTX_ADDR_MASK;
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workload->wa_ctx.indirect_ctx.size =
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(indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
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CACHELINE_BYTES;
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workload->wa_ctx.per_ctx.guest_gma =
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per_ctx & PER_CTX_ADDR_MASK;
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workload->wa_ctx.per_ctx.valid = per_ctx & 1;
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}
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gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
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workload, ring_id, head, tail, start, ctl);
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ret = prepare_mm(workload);
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if (ret) {
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kmem_cache_free(s->workloads, workload);
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return ERR_PTR(ret);
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}
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/* Only scan and shadow the first workload in the queue
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* as there is only one pre-allocated buf-obj for shadow.
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*/
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if (list_empty(workload_q_head(vgpu, ring_id))) {
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev_priv->drm.struct_mutex);
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ret = intel_gvt_scan_and_shadow_workload(workload);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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intel_runtime_pm_put(dev_priv);
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}
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if (ret && (vgpu_is_vm_unhealthy(ret))) {
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enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
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intel_vgpu_destroy_workload(workload);
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return ERR_PTR(ret);
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}
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return workload;
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}
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@ -142,7 +142,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu);
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void intel_vgpu_clean_submission(struct intel_vgpu *vgpu);
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struct intel_vgpu_workload *
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intel_vgpu_create_workload(struct intel_vgpu *vgpu);
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intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
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struct execlist_ctx_descriptor_format *desc);
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void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload);
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