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spi: sun4i: fix FIFO limit
When testing SPI without DMA I noticed that filling the FIFO on the spi controller causes timeout. Always leave room for one byte in the FIFO. Signed-off-by: Michal Suchanek <hramrach@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mark Brown <broonie@kernel.org> Cc: stable@vger.kernel.org
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1 changed files with 10 additions and 3 deletions
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@ -179,7 +179,10 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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/* We don't support transfer larger than the FIFO */
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if (tfr->len > SUN4I_FIFO_DEPTH)
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return -EINVAL;
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return -EMSGSIZE;
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if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)
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return -EMSGSIZE;
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reinit_completion(&sspi->done);
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sspi->tx_buf = tfr->tx_buf;
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@ -269,8 +272,12 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
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sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
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/* Fill the TX FIFO */
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
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/*
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* Fill the TX FIFO
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* Filling the FIFO fully causes timeout for some reason
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* at least on spi2 on A10s
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*/
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
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/* Enable the interrupts */
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
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