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arm64: Document boot requirements for SME 2
SME 2 introduces the new ZT0 register, we require that access to this reigster is not trapped when we identify that the feature is supported. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20221208-arm64-sme2-v4-2-f2fa0aef982f@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -369,6 +369,16 @@ Before jumping into the kernel, the following conditions must be met:
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- HCR_EL2.ATA (bit 56) must be initialised to 0b1.
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- HCR_EL2.ATA (bit 56) must be initialised to 0b1.
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For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2):
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- If EL3 is present:
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- SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
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- If the kernel is entered at EL1 and EL2 is present:
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- SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
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The requirements described above for CPU mode, caches, MMUs, architected
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The requirements described above for CPU mode, caches, MMUs, architected
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timers, coherency and system registers apply to all CPUs. All CPUs must
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timers, coherency and system registers apply to all CPUs. All CPUs must
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enter the kernel in the same exception level. Where the values documented
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enter the kernel in the same exception level. Where the values documented
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