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drm/amdkfd: Contain MMHUB number in mmhub_v9_4_setup_vm_pt_regs()

Browse source 
Adjust the exposed function prototype so that the caller does not need
to know the MMHUB number.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yong Zhao 2019-12-02 23:12:10 -05:00 committed by Alex Deucher
parent f275cde706
commit 6dcab16b41
4 changed files with 16 additions and 14 deletions
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6
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
View file

@ -40,7 +40,7 @@
#include "soc15d.h"
#include "mmhub_v1_0.h"
#include "gfxhub_v1_0.h"
#include "gmc_v9_0.h"
#include "mmhub_v9_4.h"
enum hqd_dequeue_request_type {
@ -774,9 +774,7 @@ void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmi
* on GFX8 and older.
*/
if (adev->asic_type == CHIP_ARCTURUS) {
/* Two MMHUBs */
mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base);
mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base);
mmhub_v9_4_setup_vm_pt_regs(adev, vmid, page_table_base);
} else
mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base);

8
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
View file

@ -36,12 +36,4 @@
extern const struct amd_ip_funcs gmc_v9_0_ip_funcs;
extern const struct amdgpu_ip_block_version gmc_v9_0_ip_block;
/* amdgpu_amdkfd*.c */
void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
uint64_t value);
void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
uint64_t value);
void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
uint32_t vmid, uint64_t value);
#endif

14
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
View file

@ -54,7 +54,7 @@ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
return base;
}
void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, int hubid,
static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
uint32_t vmid, uint64_t value)
{
/* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
@ -80,7 +80,7 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
{
uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base);
mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
WREG32_SOC15_OFFSET(MMHUB, 0,
mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
@ -101,6 +101,16 @@ static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
(u32)(adev->gmc.gart_end >> 44));
}
void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
uint64_t page_table_base)
{
int i;
for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
page_table_base);
}
static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
int hubid)
{

2
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
View file

@ -34,5 +34,7 @@ void mmhub_v9_4_init(struct amdgpu_device *adev);
int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
enum amd_clockgating_state state);
void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
uint64_t page_table_base);
#endif