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drm/amd/pp: Implement update_dpm_settings on CI
use SW method to update DPM settings by updating SRAM directly on CI. Reviewed-by: Alex Deucher <alexdeucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 97 additions and 0 deletions
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@ -2819,6 +2819,102 @@ static int ci_start_smu(struct pp_hwmgr *hwmgr)
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return 0;
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}
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static int ci_update_dpm_settings(struct pp_hwmgr *hwmgr,
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void *profile_setting)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct ci_smumgr *smu_data = (struct ci_smumgr *)
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(hwmgr->smu_backend);
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struct profile_mode_setting *setting;
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struct SMU7_Discrete_GraphicsLevel *levels =
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smu_data->smc_state_table.GraphicsLevel;
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uint32_t array = smu_data->dpm_table_start +
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offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
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uint32_t mclk_array = smu_data->dpm_table_start +
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offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
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struct SMU7_Discrete_MemoryLevel *mclk_levels =
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smu_data->smc_state_table.MemoryLevel;
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uint32_t i;
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uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
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if (profile_setting == NULL)
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return -EINVAL;
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setting = (struct profile_mode_setting *)profile_setting;
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if (setting->bupdate_sclk) {
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if (!data->sclk_dpm_key_disabled)
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
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for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
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if (levels[i].ActivityLevel !=
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cpu_to_be16(setting->sclk_activity)) {
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levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
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clk_activity_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
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+ offsetof(SMU7_Discrete_GraphicsLevel, ActivityLevel);
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offset = clk_activity_offset & ~0x3;
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tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
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tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
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}
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if (levels[i].UpH != setting->sclk_up_hyst ||
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levels[i].DownH != setting->sclk_down_hyst) {
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levels[i].UpH = setting->sclk_up_hyst;
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levels[i].DownH = setting->sclk_down_hyst;
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up_hyst_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
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+ offsetof(SMU7_Discrete_GraphicsLevel, UpH);
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down_hyst_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i)
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+ offsetof(SMU7_Discrete_GraphicsLevel, DownH);
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offset = up_hyst_offset & ~0x3;
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tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
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tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpH, sizeof(uint8_t));
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tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownH, sizeof(uint8_t));
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
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}
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}
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if (!data->sclk_dpm_key_disabled)
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
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}
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if (setting->bupdate_mclk) {
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if (!data->mclk_dpm_key_disabled)
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
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for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
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if (mclk_levels[i].ActivityLevel !=
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cpu_to_be16(setting->mclk_activity)) {
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mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
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clk_activity_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
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+ offsetof(SMU7_Discrete_MemoryLevel, ActivityLevel);
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offset = clk_activity_offset & ~0x3;
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tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
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tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
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}
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if (mclk_levels[i].UpH != setting->mclk_up_hyst ||
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mclk_levels[i].DownH != setting->mclk_down_hyst) {
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mclk_levels[i].UpH = setting->mclk_up_hyst;
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mclk_levels[i].DownH = setting->mclk_down_hyst;
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up_hyst_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
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+ offsetof(SMU7_Discrete_MemoryLevel, UpH);
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down_hyst_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i)
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+ offsetof(SMU7_Discrete_MemoryLevel, DownH);
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offset = up_hyst_offset & ~0x3;
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tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
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tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpH, sizeof(uint8_t));
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tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownH, sizeof(uint8_t));
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cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
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}
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}
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if (!data->mclk_dpm_key_disabled)
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
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}
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return 0;
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}
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const struct pp_smumgr_func ci_smu_funcs = {
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.smu_init = ci_smu_init,
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.smu_fini = ci_smu_fini,
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@ -2841,4 +2937,5 @@ const struct pp_smumgr_func ci_smu_funcs = {
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.initialize_mc_reg_table = ci_initialize_mc_reg_table,
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.is_dpm_running = ci_is_dpm_running,
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.populate_requested_graphic_levels = ci_populate_requested_graphic_levels,
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.update_dpm_settings = ci_update_dpm_settings,
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};
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