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s390: move expoline assembler macros to a header
To be able to use the expoline branches in different assembler
files move the associated macros from entry.S to a new header
nospec-insn.h.
While we are at it make the macros a bit nicer to use.
Cc: stable@vger.kernel.org # 4.16
Fixes: f19fbd5ed6
("s390: introduce execute-trampolines for branches")
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
parent
d66a735571
commit
6dd85fbb87
2 changed files with 151 additions and 81 deletions
127
arch/s390/include/asm/nospec-insn.h
Normal file
127
arch/s390/include/asm/nospec-insn.h
Normal file
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@ -0,0 +1,127 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_S390_NOSPEC_ASM_H
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#define _ASM_S390_NOSPEC_ASM_H
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#include <asm/dwarf.h>
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#ifdef __ASSEMBLY__
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#ifdef CONFIG_EXPOLINE
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/*
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* The expoline macros are used to create thunks in the same format
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* as gcc generates them. The 'comdat' section flag makes sure that
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* the various thunks are merged into a single copy.
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*/
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.macro __THUNK_PROLOG_NAME name
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.pushsection .text.\name,"axG",@progbits,\name,comdat
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.globl \name
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.hidden \name
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.type \name,@function
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\name:
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CFI_STARTPROC
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.endm
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.macro __THUNK_EPILOG
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CFI_ENDPROC
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.popsection
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.endm
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.macro __THUNK_PROLOG_BR r1,r2
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__THUNK_PROLOG_NAME __s390x_indirect_jump_r\r2\()use_r\r1
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.endm
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.macro __THUNK_BR r1,r2
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jg __s390x_indirect_jump_r\r2\()use_r\r1
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.endm
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.macro __THUNK_BRASL r1,r2,r3
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brasl \r1,__s390x_indirect_jump_r\r3\()use_r\r2
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.endm
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.macro __DECODE_RR expand,reg,ruse
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.set __decode_fail,1
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.irp r1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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.ifc \reg,%r\r1
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.irp r2,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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.ifc \ruse,%r\r2
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\expand \r1,\r2
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.set __decode_fail,0
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.endif
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.endr
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.endif
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.endr
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.if __decode_fail == 1
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.error "__DECODE_RR failed"
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.endif
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.endm
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.macro __DECODE_RRR expand,rsave,rtarget,ruse
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.set __decode_fail,1
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.irp r1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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.ifc \rsave,%r\r1
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.irp r2,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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.ifc \rtarget,%r\r2
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.irp r3,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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.ifc \ruse,%r\r3
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\expand \r1,\r2,\r3
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.set __decode_fail,0
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.endif
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.endr
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.endif
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.endr
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.endif
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.endr
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.if __decode_fail == 1
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.error "__DECODE_RRR failed"
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.endif
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.endm
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.macro __THUNK_EX_BR reg,ruse
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#ifdef CONFIG_HAVE_MARCH_Z10_FEATURES
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exrl 0,555f
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j .
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#else
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larl \ruse,555f
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ex 0,0(\ruse)
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j .
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#endif
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555: br \reg
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.endm
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.macro GEN_BR_THUNK reg,ruse=%r1
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__DECODE_RR __THUNK_PROLOG_BR,\reg,\ruse
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__THUNK_EX_BR \reg,\ruse
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__THUNK_EPILOG
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.endm
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.macro BR_EX reg,ruse=%r1
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557: __DECODE_RR __THUNK_BR,\reg,\ruse
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.pushsection .s390_indirect_branches,"a",@progbits
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.long 557b-.
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.popsection
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.endm
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.macro BASR_EX rsave,rtarget,ruse=%r1
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559: __DECODE_RRR __THUNK_BRASL,\rsave,\rtarget,\ruse
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.pushsection .s390_indirect_branches,"a",@progbits
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.long 559b-.
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.popsection
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.endm
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#else
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.macro GEN_BR_THUNK reg,ruse=%r1
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.endm
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.macro BR_EX reg,ruse=%r1
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br \reg
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.endm
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.macro BASR_EX rsave,rtarget,ruse=%r1
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basr \rsave,\rtarget
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.endm
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_S390_NOSPEC_ASM_H */
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@ -28,6 +28,7 @@
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#include <asm/setup.h>
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#include <asm/setup.h>
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#include <asm/nmi.h>
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#include <asm/nmi.h>
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#include <asm/export.h>
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#include <asm/export.h>
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#include <asm/nospec-insn.h>
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__PT_R0 = __PT_GPRS
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__PT_R0 = __PT_GPRS
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__PT_R1 = __PT_GPRS + 8
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__PT_R1 = __PT_GPRS + 8
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@ -183,67 +184,9 @@ _LPP_OFFSET = __LC_LPP
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"jnz .+8; .long 0xb2e8d000", 82
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"jnz .+8; .long 0xb2e8d000", 82
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.endm
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.endm
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#ifdef CONFIG_EXPOLINE
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GEN_BR_THUNK %r9
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GEN_BR_THUNK %r14
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.macro GEN_BR_THUNK name,reg,tmp
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GEN_BR_THUNK %r14,%r11
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.section .text.\name,"axG",@progbits,\name,comdat
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.globl \name
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.hidden \name
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.type \name,@function
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\name:
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CFI_STARTPROC
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#ifdef CONFIG_HAVE_MARCH_Z10_FEATURES
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exrl 0,0f
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#else
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larl \tmp,0f
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ex 0,0(\tmp)
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#endif
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j .
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0: br \reg
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CFI_ENDPROC
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.endm
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GEN_BR_THUNK __s390x_indirect_jump_r1use_r9,%r9,%r1
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GEN_BR_THUNK __s390x_indirect_jump_r1use_r14,%r14,%r1
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GEN_BR_THUNK __s390x_indirect_jump_r11use_r14,%r14,%r11
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.macro BASR_R14_R9
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0: brasl %r14,__s390x_indirect_jump_r1use_r9
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.pushsection .s390_indirect_branches,"a",@progbits
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.long 0b-.
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.popsection
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.endm
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.macro BR_R1USE_R14
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0: jg __s390x_indirect_jump_r1use_r14
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.pushsection .s390_indirect_branches,"a",@progbits
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.long 0b-.
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.popsection
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.endm
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.macro BR_R11USE_R14
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0: jg __s390x_indirect_jump_r11use_r14
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.pushsection .s390_indirect_branches,"a",@progbits
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.long 0b-.
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.popsection
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.endm
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#else /* CONFIG_EXPOLINE */
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.macro BASR_R14_R9
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basr %r14,%r9
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.endm
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.macro BR_R1USE_R14
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br %r14
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.endm
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.macro BR_R11USE_R14
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br %r14
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.endm
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#endif /* CONFIG_EXPOLINE */
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.section .kprobes.text, "ax"
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.section .kprobes.text, "ax"
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.Ldummy:
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.Ldummy:
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@ -260,7 +203,7 @@ _LPP_OFFSET = __LC_LPP
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ENTRY(__bpon)
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ENTRY(__bpon)
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.globl __bpon
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.globl __bpon
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BPON
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BPON
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BR_R1USE_R14
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BR_EX %r14
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/*
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/*
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* Scheduler resume function, called by switch_to
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* Scheduler resume function, called by switch_to
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@ -284,7 +227,7 @@ ENTRY(__switch_to)
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mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
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mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
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lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
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lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
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ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
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ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
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BR_R1USE_R14
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BR_EX %r14
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.L__critical_start:
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.L__critical_start:
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@ -351,7 +294,7 @@ sie_exit:
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xgr %r5,%r5
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xgr %r5,%r5
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lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
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lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
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lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
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lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
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BR_R1USE_R14
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BR_EX %r14
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.Lsie_fault:
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.Lsie_fault:
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lghi %r14,-EFAULT
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lghi %r14,-EFAULT
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stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
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stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
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@ -410,7 +353,7 @@ ENTRY(system_call)
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lgf %r9,0(%r8,%r10) # get system call add.
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lgf %r9,0(%r8,%r10) # get system call add.
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TSTMSK __TI_flags(%r12),_TIF_TRACE
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TSTMSK __TI_flags(%r12),_TIF_TRACE
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jnz .Lsysc_tracesys
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jnz .Lsysc_tracesys
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BASR_R14_R9 # call sys_xxxx
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BASR_EX %r14,%r9 # call sys_xxxx
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stg %r2,__PT_R2(%r11) # store return value
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stg %r2,__PT_R2(%r11) # store return value
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.Lsysc_return:
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.Lsysc_return:
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@ -595,7 +538,7 @@ ENTRY(system_call)
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lmg %r3,%r7,__PT_R3(%r11)
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lmg %r3,%r7,__PT_R3(%r11)
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stg %r7,STACK_FRAME_OVERHEAD(%r15)
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stg %r7,STACK_FRAME_OVERHEAD(%r15)
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lg %r2,__PT_ORIG_GPR2(%r11)
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lg %r2,__PT_ORIG_GPR2(%r11)
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BASR_R14_R9 # call sys_xxx
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BASR_EX %r14,%r9 # call sys_xxx
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stg %r2,__PT_R2(%r11) # store return value
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stg %r2,__PT_R2(%r11) # store return value
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.Lsysc_tracenogo:
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.Lsysc_tracenogo:
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TSTMSK __TI_flags(%r12),_TIF_TRACE
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TSTMSK __TI_flags(%r12),_TIF_TRACE
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@ -619,7 +562,7 @@ ENTRY(ret_from_fork)
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lmg %r9,%r10,__PT_R9(%r11) # load gprs
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lmg %r9,%r10,__PT_R9(%r11) # load gprs
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ENTRY(kernel_thread_starter)
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ENTRY(kernel_thread_starter)
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la %r2,0(%r10)
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la %r2,0(%r10)
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BASR_R14_R9
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BASR_EX %r14,%r9
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j .Lsysc_tracenogo
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j .Lsysc_tracenogo
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/*
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/*
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@ -701,7 +644,7 @@ ENTRY(pgm_check_handler)
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je .Lpgm_return
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je .Lpgm_return
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lgf %r9,0(%r10,%r1) # load address of handler routine
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lgf %r9,0(%r10,%r1) # load address of handler routine
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lgr %r2,%r11 # pass pointer to pt_regs
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lgr %r2,%r11 # pass pointer to pt_regs
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BASR_R14_R9 # branch to interrupt-handler
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BASR_EX %r14,%r9 # branch to interrupt-handler
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.Lpgm_return:
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.Lpgm_return:
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LOCKDEP_SYS_EXIT
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LOCKDEP_SYS_EXIT
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tm __PT_PSW+1(%r11),0x01 # returning to user ?
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tm __PT_PSW+1(%r11),0x01 # returning to user ?
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@ -1019,7 +962,7 @@ ENTRY(psw_idle)
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stpt __TIMER_IDLE_ENTER(%r2)
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stpt __TIMER_IDLE_ENTER(%r2)
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.Lpsw_idle_lpsw:
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.Lpsw_idle_lpsw:
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lpswe __SF_EMPTY(%r15)
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lpswe __SF_EMPTY(%r15)
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BR_R1USE_R14
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BR_EX %r14
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.Lpsw_idle_end:
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.Lpsw_idle_end:
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/*
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/*
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@ -1061,7 +1004,7 @@ ENTRY(save_fpu_regs)
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.Lsave_fpu_regs_done:
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.Lsave_fpu_regs_done:
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oi __LC_CPU_FLAGS+7,_CIF_FPU
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oi __LC_CPU_FLAGS+7,_CIF_FPU
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.Lsave_fpu_regs_exit:
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.Lsave_fpu_regs_exit:
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BR_R1USE_R14
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BR_EX %r14
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.Lsave_fpu_regs_end:
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.Lsave_fpu_regs_end:
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EXPORT_SYMBOL(save_fpu_regs)
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EXPORT_SYMBOL(save_fpu_regs)
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@ -1107,7 +1050,7 @@ load_fpu_regs:
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.Lload_fpu_regs_done:
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.Lload_fpu_regs_done:
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ni __LC_CPU_FLAGS+7,255-_CIF_FPU
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ni __LC_CPU_FLAGS+7,255-_CIF_FPU
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.Lload_fpu_regs_exit:
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.Lload_fpu_regs_exit:
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BR_R1USE_R14
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BR_EX %r14
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.Lload_fpu_regs_end:
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.Lload_fpu_regs_end:
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.L__critical_end:
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.L__critical_end:
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@ -1322,7 +1265,7 @@ cleanup_critical:
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jl 0f
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jl 0f
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clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
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clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
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jl .Lcleanup_load_fpu_regs
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jl .Lcleanup_load_fpu_regs
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0: BR_R11USE_R14
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0: BR_EX %r14
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.align 8
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.align 8
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.Lcleanup_table:
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.Lcleanup_table:
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@ -1358,7 +1301,7 @@ cleanup_critical:
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ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
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ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
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lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
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lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
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larl %r9,sie_exit # skip forward to sie_exit
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larl %r9,sie_exit # skip forward to sie_exit
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BR_R11USE_R14
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BR_EX %r14
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#endif
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#endif
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.Lcleanup_system_call:
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.Lcleanup_system_call:
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@ -1412,7 +1355,7 @@ cleanup_critical:
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stg %r15,56(%r11) # r15 stack pointer
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stg %r15,56(%r11) # r15 stack pointer
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# set new psw address and exit
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# set new psw address and exit
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||||||
larl %r9,.Lsysc_do_svc
|
larl %r9,.Lsysc_do_svc
|
||||||
BR_R11USE_R14
|
BR_EX %r14,%r11
|
||||||
.Lcleanup_system_call_insn:
|
.Lcleanup_system_call_insn:
|
||||||
.quad system_call
|
.quad system_call
|
||||||
.quad .Lsysc_stmg
|
.quad .Lsysc_stmg
|
||||||
|
@ -1424,7 +1367,7 @@ cleanup_critical:
|
||||||
|
|
||||||
.Lcleanup_sysc_tif:
|
.Lcleanup_sysc_tif:
|
||||||
larl %r9,.Lsysc_tif
|
larl %r9,.Lsysc_tif
|
||||||
BR_R11USE_R14
|
BR_EX %r14,%r11
|
||||||
|
|
||||||
.Lcleanup_sysc_restore:
|
.Lcleanup_sysc_restore:
|
||||||
# check if stpt has been executed
|
# check if stpt has been executed
|
||||||
|
@ -1441,14 +1384,14 @@ cleanup_critical:
|
||||||
mvc 0(64,%r11),__PT_R8(%r9)
|
mvc 0(64,%r11),__PT_R8(%r9)
|
||||||
lmg %r0,%r7,__PT_R0(%r9)
|
lmg %r0,%r7,__PT_R0(%r9)
|
||||||
1: lmg %r8,%r9,__LC_RETURN_PSW
|
1: lmg %r8,%r9,__LC_RETURN_PSW
|
||||||
BR_R11USE_R14
|
BR_EX %r14,%r11
|
||||||
.Lcleanup_sysc_restore_insn:
|
.Lcleanup_sysc_restore_insn:
|
||||||
.quad .Lsysc_exit_timer
|
.quad .Lsysc_exit_timer
|
||||||
.quad .Lsysc_done - 4
|
.quad .Lsysc_done - 4
|
||||||
|
|
||||||
.Lcleanup_io_tif:
|
.Lcleanup_io_tif:
|
||||||
larl %r9,.Lio_tif
|
larl %r9,.Lio_tif
|
||||||
BR_R11USE_R14
|
BR_EX %r14,%r11
|
||||||
|
|
||||||
.Lcleanup_io_restore:
|
.Lcleanup_io_restore:
|
||||||
# check if stpt has been executed
|
# check if stpt has been executed
|
||||||
|
@ -1462,7 +1405,7 @@ cleanup_critical:
|
||||||
mvc 0(64,%r11),__PT_R8(%r9)
|
mvc 0(64,%r11),__PT_R8(%r9)
|
||||||
lmg %r0,%r7,__PT_R0(%r9)
|
lmg %r0,%r7,__PT_R0(%r9)
|
||||||
1: lmg %r8,%r9,__LC_RETURN_PSW
|
1: lmg %r8,%r9,__LC_RETURN_PSW
|
||||||
BR_R11USE_R14
|
BR_EX %r14,%r11
|
||||||
.Lcleanup_io_restore_insn:
|
.Lcleanup_io_restore_insn:
|
||||||
.quad .Lio_exit_timer
|
.quad .Lio_exit_timer
|
||||||
.quad .Lio_done - 4
|
.quad .Lio_done - 4
|
||||||
|
@ -1515,17 +1458,17 @@ cleanup_critical:
|
||||||
# prepare return psw
|
# prepare return psw
|
||||||
nihh %r8,0xfcfd # clear irq & wait state bits
|
nihh %r8,0xfcfd # clear irq & wait state bits
|
||||||
lg %r9,48(%r11) # return from psw_idle
|
lg %r9,48(%r11) # return from psw_idle
|
||||||
BR_R11USE_R14
|
BR_EX %r14,%r11
|
||||||
.Lcleanup_idle_insn:
|
.Lcleanup_idle_insn:
|
||||||
.quad .Lpsw_idle_lpsw
|
.quad .Lpsw_idle_lpsw
|
||||||
|
|
||||||
.Lcleanup_save_fpu_regs:
|
.Lcleanup_save_fpu_regs:
|
||||||
larl %r9,save_fpu_regs
|
larl %r9,save_fpu_regs
|
||||||
BR_R11USE_R14
|
BR_EX %r14,%r11
|
||||||
|
|
||||||
.Lcleanup_load_fpu_regs:
|
.Lcleanup_load_fpu_regs:
|
||||||
larl %r9,load_fpu_regs
|
larl %r9,load_fpu_regs
|
||||||
BR_R11USE_R14
|
BR_EX %r14,%r11
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Integer constants
|
* Integer constants
|
||||||
|
|
Loading…
Reference in a new issue