mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-10-04 16:15:11 +00:00
Code Issues Releases Wiki Activity

media: Fix Lane mapping in Cadence CSI2TX

Browse source 
This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.

Signed-off-by: Jan Kotas <jank@cadence.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
This commit is contained in:
Jan Kotas 2019-07-22 04:22:22 -04:00 committed by Mauro Carvalho Chehab
parent bf9df90b35
commit 6ded416d4a
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
drivers/media/platform/cadence/cdns-csi2tx.c
View file

@ -236,7 +236,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx)
/* Put our lanes (clock and data) out of reset */
reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
for (i = 0; i < csi2tx->num_lanes; i++)
reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]);
reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
udelay(10);
@ -244,7 +244,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx)
/* Enable our (clock and data) lanes */
reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
for (i = 0; i < csi2tx->num_lanes; i++)
reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]);
reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
udelay(10);