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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge branch 'hns3-next'
Huazhong Tan says: ==================== code optimizations & bugfixes for HNS3 driver This patch-set includes code optimizations and bugfixes for the HNS3 ethernet controller driver. [patch 1/10] removes the redundant core reset type [patch 2/10 - 3/10] fixes two VLAN related issues [patch 4/10] fixes a TM issue [patch 5/10 - 10/10] includes some patches related to RAS & MSI-X error Change log: V1->V2: removes two patches which needs to change HNS's infiniband driver as well, they will be upstreamed later with the infiniband's one. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
6e36d77c83
11 changed files with 117 additions and 124 deletions
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@ -251,6 +251,7 @@ void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo)
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ae_algo->ops->uninit_ae_dev(ae_dev);
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hnae3_set_bit(ae_dev->flag, HNAE3_DEV_INITED_B, 0);
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ae_dev->ops = NULL;
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}
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list_del(&ae_algo->node);
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@ -351,6 +352,7 @@ void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev)
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ae_algo->ops->uninit_ae_dev(ae_dev);
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hnae3_set_bit(ae_dev->flag, HNAE3_DEV_INITED_B, 0);
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ae_dev->ops = NULL;
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}
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list_del(&ae_dev->node);
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@ -154,7 +154,6 @@ enum hnae3_reset_type {
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HNAE3_VF_FULL_RESET,
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HNAE3_FLR_RESET,
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HNAE3_FUNC_RESET,
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HNAE3_CORE_RESET,
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HNAE3_GLOBAL_RESET,
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HNAE3_IMP_RESET,
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HNAE3_UNKNOWN_RESET,
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@ -339,6 +338,8 @@ struct hnae3_ae_dev {
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* Set vlan filter config of Ports
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* set_vf_vlan_filter()
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* Set vlan filter config of vf
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* restore_vlan_table()
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* Restore vlan filter entries after reset
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* enable_hw_strip_rxvtag()
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* Enable/disable hardware strip vlan tag of packets received
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* set_gro_en
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@ -506,6 +507,7 @@ struct hnae3_ae_ops {
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void (*set_timer_task)(struct hnae3_handle *handle, bool enable);
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int (*mac_connect_phy)(struct hnae3_handle *handle);
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void (*mac_disconnect_phy)(struct hnae3_handle *handle);
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void (*restore_vlan_table)(struct hnae3_handle *handle);
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};
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struct hnae3_dcb_ops {
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@ -1548,15 +1548,11 @@ static int hns3_vlan_rx_add_vid(struct net_device *netdev,
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__be16 proto, u16 vid)
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{
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struct hnae3_handle *h = hns3_get_handle(netdev);
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struct hns3_nic_priv *priv = netdev_priv(netdev);
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int ret = -EIO;
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if (h->ae_algo->ops->set_vlan_filter)
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ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, false);
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if (!ret)
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set_bit(vid, priv->active_vlans);
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return ret;
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}
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@ -1564,33 +1560,11 @@ static int hns3_vlan_rx_kill_vid(struct net_device *netdev,
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__be16 proto, u16 vid)
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{
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struct hnae3_handle *h = hns3_get_handle(netdev);
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struct hns3_nic_priv *priv = netdev_priv(netdev);
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int ret = -EIO;
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if (h->ae_algo->ops->set_vlan_filter)
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ret = h->ae_algo->ops->set_vlan_filter(h, proto, vid, true);
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if (!ret)
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clear_bit(vid, priv->active_vlans);
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return ret;
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}
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static int hns3_restore_vlan(struct net_device *netdev)
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{
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struct hns3_nic_priv *priv = netdev_priv(netdev);
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int ret = 0;
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u16 vid;
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for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
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ret = hns3_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
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if (ret) {
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netdev_err(netdev, "Restore vlan: %d filter, ret:%d\n",
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vid, ret);
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return ret;
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}
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}
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return ret;
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}
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@ -1946,9 +1920,9 @@ static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
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if (state == pci_channel_io_perm_failure)
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return PCI_ERS_RESULT_DISCONNECT;
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if (!ae_dev) {
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if (!ae_dev || !ae_dev->ops) {
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dev_err(&pdev->dev,
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"Can't recover - error happened during device init\n");
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"Can't recover - error happened before device initialized\n");
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return PCI_ERS_RESULT_NONE;
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}
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@ -1967,6 +1941,9 @@ static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
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dev_info(dev, "requesting reset due to PCI error\n");
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if (!ae_dev || !ae_dev->ops)
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return PCI_ERS_RESULT_NONE;
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/* request the reset */
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if (ae_dev->ops->reset_event) {
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if (!ae_dev->override_pci_need_reset)
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@ -4301,12 +4278,8 @@ static int hns3_reset_notify_restore_enet(struct hnae3_handle *handle)
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vlan_filter_enable = netdev->flags & IFF_PROMISC ? false : true;
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hns3_enable_vlan_filter(netdev, vlan_filter_enable);
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/* Hardware table is only clear when pf resets */
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if (!(handle->flags & HNAE3_SUPPORT_VF)) {
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ret = hns3_restore_vlan(netdev);
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if (ret)
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return ret;
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}
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if (handle->ae_algo->ops->restore_vlan_table)
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handle->ae_algo->ops->restore_vlan_table(handle);
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return hns3_restore_fd_rules(netdev);
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}
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@ -550,7 +550,6 @@ struct hns3_nic_priv {
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struct notifier_block notifier_block;
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/* Vxlan/Geneve information */
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struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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struct hns3_enet_coalesce tx_coal;
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struct hns3_enet_coalesce rx_coal;
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};
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@ -173,7 +173,11 @@ static bool hclge_is_special_opcode(u16 opcode)
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HCLGE_OPC_STATS_MAC,
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HCLGE_OPC_STATS_MAC_ALL,
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HCLGE_OPC_QUERY_32_BIT_REG,
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HCLGE_OPC_QUERY_64_BIT_REG};
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HCLGE_OPC_QUERY_64_BIT_REG,
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HCLGE_QUERY_CLEAR_MPF_RAS_INT,
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HCLGE_QUERY_CLEAR_PF_RAS_INT,
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HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
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HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT};
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int i;
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for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
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@ -1053,7 +1053,7 @@ static void hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev)
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while (kfifo_get(&hdev->mac_tnl_log, &stats)) {
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rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS);
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dev_info(&hdev->pdev->dev, "[%07lu.%03lu]status = 0x%x\n",
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dev_info(&hdev->pdev->dev, "[%07lu.%03lu] status = 0x%x\n",
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(unsigned long)stats.time, rem_nsec / 1000,
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stats.status);
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}
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@ -87,25 +87,25 @@ static const struct hclge_hw_error hclge_msix_sram_ecc_int[] = {
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static const struct hclge_hw_error hclge_igu_int[] = {
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{ .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ /* sentinel */ }
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};
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static const struct hclge_hw_error hclge_igu_egu_tnl_int[] = {
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{ .int_msk = BIT(0), .msg = "rx_buf_overflow",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(2), .msg = "rx_stp_fifo_undeflow",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(3), .msg = "tx_buf_overflow",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(4), .msg = "tx_buf_underrun",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(5), .msg = "rx_stp_buf_overflow",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ /* sentinel */ }
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};
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@ -413,13 +413,13 @@ static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = {
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static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = {
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{ .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err",
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.reset_level = HNAE3_CORE_RESET },
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.reset_level = HNAE3_GLOBAL_RESET },
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{ /* sentinel */ }
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};
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@ -1098,8 +1098,6 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
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/* query all main PF RAS errors */
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hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_MPF_RAS_INT,
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true);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
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if (ret) {
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dev_err(dev, "query all mpf ras int cmd failed (%d)\n", ret);
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@ -1262,8 +1260,6 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
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/* clear all main PF RAS errors */
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hclge_cmd_reuse_desc(&desc[0], false);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
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if (ret)
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dev_err(dev, "clear all mpf ras int cmd failed (%d)\n", ret);
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@ -1293,8 +1289,6 @@ static int hclge_handle_pf_ras_error(struct hclge_dev *hdev,
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/* query all PF RAS errors */
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hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_PF_RAS_INT,
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true);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
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if (ret) {
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dev_err(dev, "query all pf ras int cmd failed (%d)\n", ret);
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@ -1348,8 +1342,6 @@ static int hclge_handle_pf_ras_error(struct hclge_dev *hdev,
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/* clear all PF RAS errors */
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hclge_cmd_reuse_desc(&desc[0], false);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
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if (ret)
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dev_err(dev, "clear all pf ras int cmd failed (%d)\n", ret);
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@ -1501,7 +1493,7 @@ hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev)
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return reset_type;
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}
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static int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en)
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int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en)
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{
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struct device *dev = &hdev->pdev->dev;
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struct hclge_desc desc;
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@ -1574,10 +1566,9 @@ static const struct hclge_hw_blk hw_blk[] = {
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{ /* sentinel */ }
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};
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int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state)
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int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state)
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{
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const struct hclge_hw_blk *module = hw_blk;
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struct device *dev = &hdev->pdev->dev;
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int ret = 0;
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while (module->name) {
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@ -1589,10 +1580,6 @@ int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state)
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module++;
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}
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ret = hclge_config_rocee_ras_interrupt(hdev, state);
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if (ret)
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dev_err(dev, "fail(%d) to configure ROCEE err int\n", ret);
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return ret;
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}
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@ -1667,8 +1654,6 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
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/* query all main PF MSIx errors */
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hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
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true);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], mpf_bd_num);
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if (ret) {
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dev_err(dev, "query all mpf msix int cmd failed (%d)\n",
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@ -1700,8 +1685,6 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
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/* clear all main PF MSIx errors */
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hclge_cmd_reuse_desc(&desc[0], false);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], mpf_bd_num);
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if (ret) {
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dev_err(dev, "clear all mpf msix int cmd failed (%d)\n",
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@ -1713,8 +1696,6 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
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memset(desc, 0, bd_num * sizeof(struct hclge_desc));
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hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
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true);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], pf_bd_num);
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if (ret) {
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dev_err(dev, "query all pf msix int cmd failed (%d)\n",
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@ -1753,8 +1734,6 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
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/* clear all PF MSIx errors */
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hclge_cmd_reuse_desc(&desc[0], false);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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ret = hclge_cmd_send(&hdev->hw, &desc[0], pf_bd_num);
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if (ret) {
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dev_err(dev, "clear all pf msix int cmd failed (%d)\n",
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@ -1783,7 +1762,6 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
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ret = hclge_clear_mac_tnl_int(hdev);
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if (ret)
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dev_err(dev, "clear mac tnl int failed (%d)\n", ret);
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set_bit(HNAE3_NONE_RESET, reset_requests);
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}
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msi_error:
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|
|
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@ -47,9 +47,9 @@
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#define HCLGE_NCSI_ERR_INT_TYPE 0x9
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#define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF
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#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
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#define HCLGE_MAC_TNL_INT_EN GENMASK(7, 0)
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#define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(7, 0)
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#define HCLGE_MAC_TNL_INT_CLR GENMASK(7, 0)
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#define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)
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#define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
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#define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
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@ -119,7 +119,8 @@ struct hclge_hw_error {
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};
|
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int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
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int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
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int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
|
||||
int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
|
||||
pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
|
||||
int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
|
||||
unsigned long *reset_requests);
|
||||
|
|
|
|||
|
|
@ -2706,15 +2706,6 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
|
|||
return HCLGE_VECTOR0_EVENT_RST;
|
||||
}
|
||||
|
||||
if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
|
||||
dev_info(&hdev->pdev->dev, "core reset interrupt\n");
|
||||
set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
|
||||
set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
|
||||
*clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
|
||||
hdev->rst_stats.core_rst_cnt++;
|
||||
return HCLGE_VECTOR0_EVENT_RST;
|
||||
}
|
||||
|
||||
/* check for vector0 msix event source */
|
||||
if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
|
||||
dev_dbg(&hdev->pdev->dev, "received event 0x%x\n",
|
||||
|
|
@ -2941,10 +2932,6 @@ static int hclge_reset_wait(struct hclge_dev *hdev)
|
|||
reg = HCLGE_GLOBAL_RESET_REG;
|
||||
reg_bit = HCLGE_GLOBAL_RESET_BIT;
|
||||
break;
|
||||
case HNAE3_CORE_RESET:
|
||||
reg = HCLGE_GLOBAL_RESET_REG;
|
||||
reg_bit = HCLGE_CORE_RESET_BIT;
|
||||
break;
|
||||
case HNAE3_FUNC_RESET:
|
||||
reg = HCLGE_FUN_RST_ING;
|
||||
reg_bit = HCLGE_FUN_RST_ING_B;
|
||||
|
|
@ -3076,12 +3063,6 @@ static void hclge_do_reset(struct hclge_dev *hdev)
|
|||
hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
|
||||
dev_info(&pdev->dev, "Global Reset requested\n");
|
||||
break;
|
||||
case HNAE3_CORE_RESET:
|
||||
val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
|
||||
hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
|
||||
hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
|
||||
dev_info(&pdev->dev, "Core Reset requested\n");
|
||||
break;
|
||||
case HNAE3_FUNC_RESET:
|
||||
dev_info(&pdev->dev, "PF Reset requested\n");
|
||||
/* schedule again to check later */
|
||||
|
|
@ -3128,16 +3109,10 @@ static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
|
|||
rst_level = HNAE3_IMP_RESET;
|
||||
clear_bit(HNAE3_IMP_RESET, addr);
|
||||
clear_bit(HNAE3_GLOBAL_RESET, addr);
|
||||
clear_bit(HNAE3_CORE_RESET, addr);
|
||||
clear_bit(HNAE3_FUNC_RESET, addr);
|
||||
} else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
|
||||
rst_level = HNAE3_GLOBAL_RESET;
|
||||
clear_bit(HNAE3_GLOBAL_RESET, addr);
|
||||
clear_bit(HNAE3_CORE_RESET, addr);
|
||||
clear_bit(HNAE3_FUNC_RESET, addr);
|
||||
} else if (test_bit(HNAE3_CORE_RESET, addr)) {
|
||||
rst_level = HNAE3_CORE_RESET;
|
||||
clear_bit(HNAE3_CORE_RESET, addr);
|
||||
clear_bit(HNAE3_FUNC_RESET, addr);
|
||||
} else if (test_bit(HNAE3_FUNC_RESET, addr)) {
|
||||
rst_level = HNAE3_FUNC_RESET;
|
||||
|
|
@ -3165,9 +3140,6 @@ static void hclge_clear_reset_cause(struct hclge_dev *hdev)
|
|||
case HNAE3_GLOBAL_RESET:
|
||||
clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
|
||||
break;
|
||||
case HNAE3_CORE_RESET:
|
||||
clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -7053,6 +7025,12 @@ static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
|
|||
u8 vf_byte_off;
|
||||
int ret;
|
||||
|
||||
/* if vf vlan table is full, firmware will close vf vlan filter, it
|
||||
* is unable and unnecessary to add new vlan id to vf vlan filter
|
||||
*/
|
||||
if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill)
|
||||
return 0;
|
||||
|
||||
hclge_cmd_setup_basic_desc(&desc[0],
|
||||
HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
|
||||
hclge_cmd_setup_basic_desc(&desc[1],
|
||||
|
|
@ -7088,6 +7066,7 @@ static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
|
|||
return 0;
|
||||
|
||||
if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
|
||||
set_bit(vfid, hdev->vf_vlan_full);
|
||||
dev_warn(&hdev->pdev->dev,
|
||||
"vf vlan table is full, vf vlan filter is disabled\n");
|
||||
return 0;
|
||||
|
|
@ -7422,10 +7401,6 @@ static void hclge_add_vport_vlan_table(struct hclge_vport *vport, u16 vlan_id,
|
|||
{
|
||||
struct hclge_vport_vlan_cfg *vlan;
|
||||
|
||||
/* vlan 0 is reserved */
|
||||
if (!vlan_id)
|
||||
return;
|
||||
|
||||
vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
|
||||
if (!vlan)
|
||||
return;
|
||||
|
|
@ -7520,6 +7495,43 @@ void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev)
|
|||
mutex_unlock(&hdev->vport_cfg_mutex);
|
||||
}
|
||||
|
||||
static void hclge_restore_vlan_table(struct hnae3_handle *handle)
|
||||
{
|
||||
struct hclge_vport *vport = hclge_get_vport(handle);
|
||||
struct hclge_vport_vlan_cfg *vlan, *tmp;
|
||||
struct hclge_dev *hdev = vport->back;
|
||||
u16 vlan_proto, qos;
|
||||
u16 state, vlan_id;
|
||||
int i;
|
||||
|
||||
mutex_lock(&hdev->vport_cfg_mutex);
|
||||
for (i = 0; i < hdev->num_alloc_vport; i++) {
|
||||
vport = &hdev->vport[i];
|
||||
vlan_proto = vport->port_base_vlan_cfg.vlan_info.vlan_proto;
|
||||
vlan_id = vport->port_base_vlan_cfg.vlan_info.vlan_tag;
|
||||
qos = vport->port_base_vlan_cfg.vlan_info.qos;
|
||||
state = vport->port_base_vlan_cfg.state;
|
||||
|
||||
if (state != HNAE3_PORT_BASE_VLAN_DISABLE) {
|
||||
hclge_set_vlan_filter_hw(hdev, htons(vlan_proto),
|
||||
vport->vport_id, vlan_id, qos,
|
||||
false);
|
||||
continue;
|
||||
}
|
||||
|
||||
list_for_each_entry_safe(vlan, tmp, &vport->vlan_list, node) {
|
||||
if (vlan->hd_tbl_status)
|
||||
hclge_set_vlan_filter_hw(hdev,
|
||||
htons(ETH_P_8021Q),
|
||||
vport->vport_id,
|
||||
vlan->vlan_id, 0,
|
||||
false);
|
||||
}
|
||||
}
|
||||
|
||||
mutex_unlock(&hdev->vport_cfg_mutex);
|
||||
}
|
||||
|
||||
int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
|
||||
{
|
||||
struct hclge_vport *vport = hclge_get_vport(handle);
|
||||
|
|
@ -8190,10 +8202,16 @@ static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev,
|
|||
set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
|
||||
hnae3_set_client_init_flag(client, ae_dev, 1);
|
||||
|
||||
/* Enable nic hw error interrupts */
|
||||
ret = hclge_config_nic_hw_error(hdev, true);
|
||||
if (ret)
|
||||
dev_err(&ae_dev->pdev->dev,
|
||||
"fail(%d) to enable hw error interrupts\n", ret);
|
||||
|
||||
if (netif_msg_drv(&hdev->vport->nic))
|
||||
hclge_info_show(hdev);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
|
||||
|
|
@ -8273,7 +8291,13 @@ static int hclge_init_client_instance(struct hnae3_client *client,
|
|||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
/* Enable roce ras interrupts */
|
||||
ret = hclge_config_rocee_ras_interrupt(hdev, true);
|
||||
if (ret)
|
||||
dev_err(&ae_dev->pdev->dev,
|
||||
"fail(%d) to enable roce ras interrupts\n", ret);
|
||||
|
||||
return ret;
|
||||
|
||||
clear_nic:
|
||||
hdev->nic_client = NULL;
|
||||
|
|
@ -8577,13 +8601,6 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
|
|||
goto err_mdiobus_unreg;
|
||||
}
|
||||
|
||||
ret = hclge_hw_error_set_state(hdev, true);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"fail(%d) to enable hw error interrupts\n", ret);
|
||||
goto err_mdiobus_unreg;
|
||||
}
|
||||
|
||||
INIT_KFIFO(hdev->mac_tnl_log);
|
||||
|
||||
hclge_dcb_ops_set(hdev);
|
||||
|
|
@ -8649,6 +8666,7 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
|
|||
|
||||
hclge_stats_clear(hdev);
|
||||
memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
|
||||
memset(hdev->vf_vlan_full, 0, sizeof(hdev->vf_vlan_full));
|
||||
|
||||
ret = hclge_cmd_init(hdev);
|
||||
if (ret) {
|
||||
|
|
@ -8706,15 +8724,26 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
|
|||
}
|
||||
|
||||
/* Re-enable the hw error interrupts because
|
||||
* the interrupts get disabled on core/global reset.
|
||||
* the interrupts get disabled on global reset.
|
||||
*/
|
||||
ret = hclge_hw_error_set_state(hdev, true);
|
||||
ret = hclge_config_nic_hw_error(hdev, true);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"fail(%d) to re-enable HNS hw error interrupts\n", ret);
|
||||
"fail(%d) to re-enable NIC hw error interrupts\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (hdev->roce_client) {
|
||||
ret = hclge_config_rocee_ras_interrupt(hdev, true);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"fail(%d) to re-enable roce ras interrupts\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
hclge_reset_vport_state(hdev);
|
||||
|
||||
dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
|
||||
|
|
@ -8739,8 +8768,11 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
|
|||
hclge_enable_vector(&hdev->misc_vector, false);
|
||||
synchronize_irq(hdev->misc_vector.vector_irq);
|
||||
|
||||
/* Disable all hw interrupts */
|
||||
hclge_config_mac_tnl_int(hdev, false);
|
||||
hclge_hw_error_set_state(hdev, false);
|
||||
hclge_config_nic_hw_error(hdev, false);
|
||||
hclge_config_rocee_ras_interrupt(hdev, false);
|
||||
|
||||
hclge_cmd_uninit(hdev);
|
||||
hclge_misc_irq_uninit(hdev);
|
||||
hclge_pci_uninit(hdev);
|
||||
|
|
@ -9226,6 +9258,7 @@ static const struct hnae3_ae_ops hclge_ops = {
|
|||
.set_timer_task = hclge_set_timer_task,
|
||||
.mac_connect_phy = hclge_mac_connect_phy,
|
||||
.mac_disconnect_phy = hclge_mac_disconnect_phy,
|
||||
.restore_vlan_table = hclge_restore_vlan_table,
|
||||
};
|
||||
|
||||
static struct hnae3_ae_algo ae_algo = {
|
||||
|
|
|
|||
|
|
@ -820,6 +820,7 @@ struct hclge_dev {
|
|||
struct hclge_vlan_type_cfg vlan_type_cfg;
|
||||
|
||||
unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
|
||||
unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
|
||||
|
||||
struct hclge_fd_cfg fd_cfg;
|
||||
struct hlist_head fd_rule_list;
|
||||
|
|
|
|||
|
|
@ -397,7 +397,7 @@ static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
|
|||
u8 ir_u, ir_b, ir_s;
|
||||
int ret;
|
||||
|
||||
ret = hclge_shaper_para_calc(HCLGE_ETHER_MAX_RATE,
|
||||
ret = hclge_shaper_para_calc(hdev->hw.mac.speed,
|
||||
HCLGE_SHAPER_LVL_PORT,
|
||||
&ir_b, &ir_u, &ir_s);
|
||||
if (ret)
|
||||
|
|
|
|||
Loading…
Reference in a new issue