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drm/i915: All fw_domains share the same set/clear/reset values
Since we reuse the same values for each fw_domain, move them onto uncore. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170323101944.21627-6-chris@chris-wilson.co.uk
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parent
0f966aaf5f
commit
6e3955a5af
2 changed files with 27 additions and 24 deletions
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@ -774,16 +774,17 @@ struct intel_uncore {
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enum forcewake_domains fw_domains;
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enum forcewake_domains fw_domains_active;
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u32 fw_set;
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u32 fw_clear;
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u32 fw_reset;
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struct intel_uncore_forcewake_domain {
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enum forcewake_domain_id id;
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enum forcewake_domains mask;
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unsigned wake_count;
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struct hrtimer timer;
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i915_reg_t reg_set;
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u32 val_set;
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u32 val_clear;
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i915_reg_t reg_ack;
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u32 val_reset;
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} fw_domain[FW_DOMAIN_ID_COUNT];
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int unclaimed_mmio_check;
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@ -3956,14 +3957,14 @@ u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
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#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
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#define __raw_read(x, s) \
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static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
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static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
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i915_reg_t reg) \
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{ \
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return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
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}
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#define __raw_write(x, s) \
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static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
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static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
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i915_reg_t reg, uint##x##_t val) \
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{ \
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write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
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@ -55,8 +55,7 @@ static inline void
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fw_domain_reset(struct drm_i915_private *i915,
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const struct intel_uncore_forcewake_domain *d)
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{
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WARN_ON(!i915_mmio_reg_valid(d->reg_set));
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__raw_i915_write32(i915, d->reg_set, d->val_reset);
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__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset);
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}
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static inline void
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@ -70,7 +69,7 @@ fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
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}
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static inline void
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fw_domain_wait_ack_clear(struct drm_i915_private *i915,
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fw_domain_wait_ack_clear(const struct drm_i915_private *i915,
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const struct intel_uncore_forcewake_domain *d)
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{
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if (wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) &
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@ -84,11 +83,11 @@ static inline void
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fw_domain_get(struct drm_i915_private *i915,
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const struct intel_uncore_forcewake_domain *d)
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{
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__raw_i915_write32(i915, d->reg_set, d->val_set);
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__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_set);
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}
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static inline void
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fw_domain_wait_ack(struct drm_i915_private *i915,
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fw_domain_wait_ack(const struct drm_i915_private *i915,
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const struct intel_uncore_forcewake_domain *d)
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{
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if (wait_for_atomic((__raw_i915_read32(i915, d->reg_ack) &
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@ -99,10 +98,10 @@ fw_domain_wait_ack(struct drm_i915_private *i915,
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}
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static inline void
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fw_domain_put(struct drm_i915_private *i915,
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fw_domain_put(const struct drm_i915_private *i915,
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const struct intel_uncore_forcewake_domain *d)
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{
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__raw_i915_write32(i915, d->reg_set, d->val_clear);
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__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_clear);
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}
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static void
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@ -1139,21 +1138,13 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
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WARN_ON(d->wake_count);
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WARN_ON(!i915_mmio_reg_valid(reg_set));
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WARN_ON(!i915_mmio_reg_valid(reg_ack));
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d->wake_count = 0;
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d->reg_set = reg_set;
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d->reg_ack = reg_ack;
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if (IS_GEN6(dev_priv)) {
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d->val_reset = 0;
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d->val_set = FORCEWAKE_KERNEL;
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d->val_clear = 0;
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} else {
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/* WaRsClearFWBitsAtReset:bdw,skl */
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d->val_reset = _MASKED_BIT_DISABLE(0xffff);
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d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
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d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
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}
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d->id = domain_id;
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BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
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@ -1165,7 +1156,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
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hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
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d->timer.function = intel_uncore_fw_release_timer;
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dev_priv->uncore.fw_domains |= (1 << domain_id);
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dev_priv->uncore.fw_domains |= BIT(domain_id);
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fw_domain_reset(dev_priv, d);
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}
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@ -1175,6 +1166,17 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
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if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
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return;
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if (IS_GEN6(dev_priv)) {
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dev_priv->uncore.fw_reset = 0;
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dev_priv->uncore.fw_set = FORCEWAKE_KERNEL;
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dev_priv->uncore.fw_clear = 0;
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} else {
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/* WaRsClearFWBitsAtReset:bdw,skl */
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dev_priv->uncore.fw_reset = _MASKED_BIT_DISABLE(0xffff);
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dev_priv->uncore.fw_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
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dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
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}
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if (IS_GEN9(dev_priv)) {
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dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
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dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
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