net: phy: add Marvell 88X2222 transceiver support
Add basic support for the Marvell 88X2222 multi-speed ethernet transceiver. This PHY provides data transmission over fiber-optic as well as Twinax copper links. The 88X2222 supports 2 ports of 10GBase-R and 1000Base-X on the line-side interface. The host-side interface supports 4 ports of 10GBase-R, RXAUI, 1000Base-X and 2 ports of XAUI. This driver, however, supports only XAUI on the host-side and 1000Base-X/10GBase-R on the line-side, for now. The SGMII is also supported over 1000Base-X. Interrupts are not supported. Internal registers access compliant with the Clause 45 specification. Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ivan Bornyakov
David S. Miller
parent
63fe60596b
commit
6e3bac3eba
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@ -201,6 +201,12 @@ config MARVELL_10G_PHY
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help
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Support for the Marvell Alaska MV88X3310 and compatible PHYs.
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config MARVELL_88X2222_PHY
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tristate "Marvell 88X2222 PHY"
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help
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Support for the Marvell 88X2222 Dual-port Multi-speed Ethernet
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Transceiver.
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config MICREL_PHY
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tristate "Micrel PHYs"
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help
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@ -63,6 +63,7 @@ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
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obj-$(CONFIG_LXT_PHY) += lxt.o
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obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o
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obj-$(CONFIG_MARVELL_PHY) += marvell.o
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obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
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obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
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obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
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obj-$(CONFIG_MICREL_PHY) += micrel.o
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@ -0,0 +1,519 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell 88x2222 dual-port multi-speed ethernet transceiver.
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*
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* Supports:
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* XAUI on the host side.
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* 1000Base-X or 10GBase-R on the line side.
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* SGMII over 1000Base-X.
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*/
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/mdio.h>
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#include <linux/marvell_phy.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/sfp.h>
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#include <linux/netdevice.h>
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/* Port PCS Configuration */
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#define MV_PCS_CONFIG 0xF002
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#define MV_PCS_HOST_XAUI 0x73
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#define MV_PCS_LINE_10GBR (0x71 << 8)
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#define MV_PCS_LINE_1GBX_AN (0x7B << 8)
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#define MV_PCS_LINE_SGMII_AN (0x7F << 8)
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/* Port Reset and Power Down */
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#define MV_PORT_RST 0xF003
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#define MV_LINE_RST_SW BIT(15)
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#define MV_HOST_RST_SW BIT(7)
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#define MV_PORT_RST_SW (MV_LINE_RST_SW | MV_HOST_RST_SW)
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/* 1000Base-X/SGMII Control Register */
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#define MV_1GBX_CTRL (0x2000 + MII_BMCR)
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/* 1000BASE-X/SGMII Status Register */
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#define MV_1GBX_STAT (0x2000 + MII_BMSR)
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/* 1000Base-X Auto-Negotiation Advertisement Register */
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#define MV_1GBX_ADVERTISE (0x2000 + MII_ADVERTISE)
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/* 1000Base-X PHY Specific Status Register */
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#define MV_1GBX_PHY_STAT 0xA003
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#define MV_1GBX_PHY_STAT_AN_RESOLVED BIT(11)
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#define MV_1GBX_PHY_STAT_DUPLEX BIT(13)
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#define MV_1GBX_PHY_STAT_SPEED100 BIT(14)
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#define MV_1GBX_PHY_STAT_SPEED1000 BIT(15)
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struct mv2222_data {
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phy_interface_t line_interface;
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__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
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};
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/* SFI PMA transmit enable */
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static int mv2222_tx_enable(struct phy_device *phydev)
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{
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return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
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MDIO_PMD_TXDIS_GLOBAL);
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}
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/* SFI PMA transmit disable */
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static int mv2222_tx_disable(struct phy_device *phydev)
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{
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return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
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MDIO_PMD_TXDIS_GLOBAL);
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}
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static int mv2222_soft_reset(struct phy_device *phydev)
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{
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int val, ret;
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ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST,
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MV_PORT_RST_SW);
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if (ret < 0)
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return ret;
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return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST,
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val, !(val & MV_PORT_RST_SW),
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5000, 1000000, true);
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}
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/* Returns negative on error, 0 if link is down, 1 if link is up */
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static int mv2222_read_status_10g(struct phy_device *phydev)
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{
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int val, link = 0;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
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if (val < 0)
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return val;
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if (val & MDIO_STAT1_LSTATUS) {
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link = 1;
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/* 10GBASE-R do not support auto-negotiation */
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phydev->autoneg = AUTONEG_DISABLE;
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phydev->speed = SPEED_10000;
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phydev->duplex = DUPLEX_FULL;
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}
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return link;
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}
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/* Returns negative on error, 0 if link is down, 1 if link is up */
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static int mv2222_read_status_1g(struct phy_device *phydev)
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{
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int val, link = 0;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT);
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if (val < 0)
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return val;
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if (!(val & BMSR_LSTATUS) ||
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(phydev->autoneg == AUTONEG_ENABLE &&
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!(val & BMSR_ANEGCOMPLETE)))
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return 0;
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link = 1;
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val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_PHY_STAT);
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if (val < 0)
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return val;
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if (val & MV_1GBX_PHY_STAT_AN_RESOLVED) {
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if (val & MV_1GBX_PHY_STAT_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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if (val & MV_1GBX_PHY_STAT_SPEED1000)
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phydev->speed = SPEED_1000;
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else if (val & MV_1GBX_PHY_STAT_SPEED100)
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phydev->speed = SPEED_100;
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else
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phydev->speed = SPEED_10;
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}
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return link;
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}
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static int mv2222_read_status(struct phy_device *phydev)
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{
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struct mv2222_data *priv = phydev->priv;
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int link;
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phydev->link = 0;
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phydev->speed = SPEED_UNKNOWN;
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phydev->duplex = DUPLEX_UNKNOWN;
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if (priv->line_interface == PHY_INTERFACE_MODE_10GBASER)
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link = mv2222_read_status_10g(phydev);
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else
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link = mv2222_read_status_1g(phydev);
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if (link < 0)
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return link;
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phydev->link = link;
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return 0;
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}
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static int mv2222_disable_aneg(struct phy_device *phydev)
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{
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int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
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BMCR_ANENABLE | BMCR_ANRESTART);
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if (ret < 0)
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return ret;
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return mv2222_soft_reset(phydev);
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}
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static int mv2222_enable_aneg(struct phy_device *phydev)
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{
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int ret = phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL,
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BMCR_ANENABLE | BMCR_RESET);
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if (ret < 0)
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return ret;
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return mv2222_soft_reset(phydev);
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}
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static int mv2222_set_sgmii_speed(struct phy_device *phydev)
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{
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struct mv2222_data *priv = phydev->priv;
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switch (phydev->speed) {
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default:
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case SPEED_1000:
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if ((linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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priv->supported) ||
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linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
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priv->supported)))
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return phy_modify_mmd(phydev, MDIO_MMD_PCS,
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MV_1GBX_CTRL,
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BMCR_SPEED1000 | BMCR_SPEED100,
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BMCR_SPEED1000);
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fallthrough;
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case SPEED_100:
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if ((linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
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priv->supported) ||
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linkmode_test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
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priv->supported)))
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return phy_modify_mmd(phydev, MDIO_MMD_PCS,
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MV_1GBX_CTRL,
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BMCR_SPEED1000 | BMCR_SPEED100,
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BMCR_SPEED100);
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fallthrough;
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case SPEED_10:
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if ((linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
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priv->supported) ||
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linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
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priv->supported)))
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return phy_modify_mmd(phydev, MDIO_MMD_PCS,
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MV_1GBX_CTRL,
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BMCR_SPEED1000 | BMCR_SPEED100,
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BMCR_SPEED10);
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return -EINVAL;
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}
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}
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static bool mv2222_is_10g_capable(struct phy_device *phydev)
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{
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struct mv2222_data *priv = phydev->priv;
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return (linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
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priv->supported) ||
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linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
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priv->supported) ||
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linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
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priv->supported) ||
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linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
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priv->supported) ||
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linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
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priv->supported) ||
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linkmode_test_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
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priv->supported));
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}
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static bool mv2222_is_1gbx_capable(struct phy_device *phydev)
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{
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struct mv2222_data *priv = phydev->priv;
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return linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
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priv->supported);
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}
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static int mv2222_config_line(struct phy_device *phydev)
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{
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struct mv2222_data *priv = phydev->priv;
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switch (priv->line_interface) {
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case PHY_INTERFACE_MODE_10GBASER:
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return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
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MV_PCS_HOST_XAUI | MV_PCS_LINE_10GBR);
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case PHY_INTERFACE_MODE_1000BASEX:
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return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
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MV_PCS_HOST_XAUI | MV_PCS_LINE_1GBX_AN);
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case PHY_INTERFACE_MODE_SGMII:
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return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG,
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MV_PCS_HOST_XAUI | MV_PCS_LINE_SGMII_AN);
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default:
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return -EINVAL;
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}
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}
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static int mv2222_setup_forced(struct phy_device *phydev)
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{
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struct mv2222_data *priv = phydev->priv;
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bool changed = false;
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int ret;
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switch (priv->line_interface) {
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case PHY_INTERFACE_MODE_10GBASER:
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if (phydev->speed == SPEED_1000 &&
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mv2222_is_1gbx_capable(phydev)) {
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priv->line_interface = PHY_INTERFACE_MODE_1000BASEX;
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changed = true;
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}
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break;
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case PHY_INTERFACE_MODE_1000BASEX:
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if (phydev->speed == SPEED_10000 &&
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mv2222_is_10g_capable(phydev)) {
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priv->line_interface = PHY_INTERFACE_MODE_10GBASER;
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changed = true;
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}
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break;
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case PHY_INTERFACE_MODE_SGMII:
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ret = mv2222_set_sgmii_speed(phydev);
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if (ret < 0)
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return ret;
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break;
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default:
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return -EINVAL;
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}
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if (changed) {
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ret = mv2222_config_line(phydev);
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if (ret < 0)
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return ret;
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}
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return mv2222_disable_aneg(phydev);
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}
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static int mv2222_config_aneg(struct phy_device *phydev)
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{
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struct mv2222_data *priv = phydev->priv;
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int ret, adv;
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/* SFP is not present, do nothing */
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if (priv->line_interface == PHY_INTERFACE_MODE_NA)
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return 0;
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if (phydev->autoneg == AUTONEG_DISABLE ||
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phydev->speed == SPEED_10000)
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return mv2222_setup_forced(phydev);
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if (priv->line_interface == PHY_INTERFACE_MODE_10GBASER &&
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mv2222_is_1gbx_capable(phydev)) {
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priv->line_interface = PHY_INTERFACE_MODE_1000BASEX;
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ret = mv2222_config_line(phydev);
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if (ret < 0)
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return ret;
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}
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adv = linkmode_adv_to_mii_adv_x(priv->supported,
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ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
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ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_ADVERTISE,
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ADVERTISE_1000XFULL |
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ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
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adv);
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if (ret < 0)
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return ret;
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return mv2222_enable_aneg(phydev);
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}
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static int mv2222_aneg_done(struct phy_device *phydev)
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{
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int ret;
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if (mv2222_is_10g_capable(phydev)) {
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ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
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if (ret < 0)
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return ret;
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if (ret & MDIO_STAT1_LSTATUS)
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return 1;
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}
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ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_STAT);
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if (ret < 0)
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return ret;
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return (ret & BMSR_ANEGCOMPLETE);
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}
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static int mv2222_resume(struct phy_device *phydev)
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{
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return mv2222_tx_enable(phydev);
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}
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static int mv2222_suspend(struct phy_device *phydev)
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{
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return mv2222_tx_disable(phydev);
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}
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static int mv2222_get_features(struct phy_device *phydev)
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{
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/* All supported linkmodes are set at probe */
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return 0;
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}
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static int mv2222_config_init(struct phy_device *phydev)
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{
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if (phydev->interface != PHY_INTERFACE_MODE_XAUI)
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return -EINVAL;
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phydev->autoneg = AUTONEG_DISABLE;
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return 0;
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}
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static int mv2222_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
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{
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struct phy_device *phydev = upstream;
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phy_interface_t sfp_interface;
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struct mv2222_data *priv;
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struct device *dev;
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int ret;
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__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_supported) = { 0, };
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priv = (struct mv2222_data *)phydev->priv;
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dev = &phydev->mdio.dev;
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sfp_parse_support(phydev->sfp_bus, id, sfp_supported);
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sfp_interface = sfp_select_interface(phydev->sfp_bus, sfp_supported);
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dev_info(dev, "%s SFP module inserted\n", phy_modes(sfp_interface));
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if (sfp_interface != PHY_INTERFACE_MODE_10GBASER &&
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sfp_interface != PHY_INTERFACE_MODE_1000BASEX &&
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sfp_interface != PHY_INTERFACE_MODE_SGMII) {
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dev_err(dev, "Incompatible SFP module inserted\n");
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return -EINVAL;
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}
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priv->line_interface = sfp_interface;
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linkmode_and(priv->supported, phydev->supported, sfp_supported);
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ret = mv2222_config_line(phydev);
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if (ret < 0)
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return ret;
|
||||
|
||||
if (mutex_trylock(&phydev->lock)) {
|
||||
if (priv->line_interface == PHY_INTERFACE_MODE_10GBASER)
|
||||
ret = mv2222_setup_forced(phydev);
|
||||
else
|
||||
ret = mv2222_config_aneg(phydev);
|
||||
|
||||
mutex_unlock(&phydev->lock);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mv2222_sfp_remove(void *upstream)
|
||||
{
|
||||
struct phy_device *phydev = upstream;
|
||||
struct mv2222_data *priv;
|
||||
|
||||
priv = (struct mv2222_data *)phydev->priv;
|
||||
|
||||
priv->line_interface = PHY_INTERFACE_MODE_NA;
|
||||
linkmode_zero(priv->supported);
|
||||
}
|
||||
|
||||
static const struct sfp_upstream_ops sfp_phy_ops = {
|
||||
.module_insert = mv2222_sfp_insert,
|
||||
.module_remove = mv2222_sfp_remove,
|
||||
.attach = phy_sfp_attach,
|
||||
.detach = phy_sfp_detach,
|
||||
};
|
||||
|
||||
static int mv2222_probe(struct phy_device *phydev)
|
||||
{
|
||||
struct device *dev = &phydev->mdio.dev;
|
||||
struct mv2222_data *priv = NULL;
|
||||
|
||||
__ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
|
||||
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT, supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
|
||||
|
||||
linkmode_copy(phydev->supported, supported);
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->line_interface = PHY_INTERFACE_MODE_NA;
|
||||
phydev->priv = priv;
|
||||
|
||||
return phy_sfp_probe(phydev, &sfp_phy_ops);
|
||||
}
|
||||
|
||||
static struct phy_driver mv2222_drivers[] = {
|
||||
{
|
||||
.phy_id = MARVELL_PHY_ID_88X2222,
|
||||
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
||||
.name = "Marvell 88X2222",
|
||||
.get_features = mv2222_get_features,
|
||||
.soft_reset = mv2222_soft_reset,
|
||||
.config_init = mv2222_config_init,
|
||||
.config_aneg = mv2222_config_aneg,
|
||||
.aneg_done = mv2222_aneg_done,
|
||||
.probe = mv2222_probe,
|
||||
.suspend = mv2222_suspend,
|
||||
.resume = mv2222_resume,
|
||||
.read_status = mv2222_read_status,
|
||||
},
|
||||
};
|
||||
module_phy_driver(mv2222_drivers);
|
||||
|
||||
static struct mdio_device_id __maybe_unused mv2222_tbl[] = {
|
||||
{ MARVELL_PHY_ID_88X2222, MARVELL_PHY_ID_MASK },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(mdio, mv2222_tbl);
|
||||
|
||||
MODULE_DESCRIPTION("Marvell 88x2222 ethernet transceiver driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
#define MARVELL_PHY_ID_88E3016 0x01410e60
|
||||
#define MARVELL_PHY_ID_88X3310 0x002b09a0
|
||||
#define MARVELL_PHY_ID_88E2110 0x002b09b0
|
||||
#define MARVELL_PHY_ID_88X2222 0x01410f10
|
||||
|
||||
/* Marvel 88E1111 in Finisar SFP module with modified PHY ID */
|
||||
#define MARVELL_PHY_ID_88E1111_FINISAR 0x01ff0cc0
|
||||
|
|
|
|||
Loading…
Reference in New Issue