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mtd: m25p80: re-align ID entries
No change in the table data. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
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1a874e9101
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6e5d9bda27
1 changed files with 16 additions and 16 deletions
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@ -740,19 +740,19 @@ static const struct spi_device_id m25p_ids[] = {
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{ "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
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/* EON -- en25xxx */
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{ "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
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{ "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
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{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
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{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
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{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
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{ "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
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{ "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
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{ "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
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{ "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
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{ "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
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{ "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
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{ "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
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/* ESMT */
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{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
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/* Everspin */
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{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
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{ "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
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{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
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{ "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
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/* GigaDevice */
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{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
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@ -777,16 +777,16 @@ static const struct spi_device_id m25p_ids[] = {
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{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, 0) },
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/* Micron */
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{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
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{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
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{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
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{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
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{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
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{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
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{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
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{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
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{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
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{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
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/* PMC */
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{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
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{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
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{ "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
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{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
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{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
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{ "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
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/* Spansion -- single (large) sector size only, at least
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* for the chips listed here (without boot sectors).
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