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drm/nouveau: Fix a couple of sparse warnings.
Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
2ed06b7d97
commit
6e86e04194
9 changed files with 20 additions and 19 deletions
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@ -42,7 +42,7 @@ static const char nouveau_dsm_muid[] = {
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0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4,
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};
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static int nouveau_dsm(acpi_handle handle, int func, int arg, int *result)
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static int nouveau_dsm(acpi_handle handle, int func, int arg, uint32_t *result)
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{
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struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
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struct acpi_object_list input;
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@ -585,7 +585,6 @@ nouveau_connector_get_modes(struct drm_connector *connector)
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_connector *nv_connector = nouveau_connector(connector);
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struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
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struct drm_display_mode mode;
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int ret = 0;
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/* destroy the native mode, the attached monitor could have changed.
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@ -600,9 +599,9 @@ nouveau_connector_get_modes(struct drm_connector *connector)
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else
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if (nv_encoder->dcb->type == OUTPUT_LVDS &&
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(nv_encoder->dcb->lvdsconf.use_straps_for_mode ||
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dev_priv->vbios.fp_no_ddc) &&
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nouveau_bios_fp_mode(dev, &mode)) {
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nv_connector->native_mode = drm_mode_duplicate(dev, &mode);
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dev_priv->vbios.fp_no_ddc) && nouveau_bios_fp_mode(dev, NULL)) {
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nv_connector->native_mode = drm_mode_create(dev);
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nouveau_bios_fp_mode(dev, nv_connector->native_mode);
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}
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/* Find the native mode if this is a digital panel, if we didn't
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@ -317,7 +317,6 @@ nouveau_pci_resume(struct pci_dev *pdev)
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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int ret;
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ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
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if (!ret)
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@ -333,7 +333,7 @@ nouveau_fbcon_output_poll_changed(struct drm_device *dev)
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drm_fb_helper_hotplug_event(&dev_priv->nfbdev->helper);
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}
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int
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static int
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nouveau_fbcon_destroy(struct drm_device *dev, struct nouveau_fbdev *nfbdev)
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{
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struct nouveau_framebuffer *nouveau_fb = &nfbdev->nouveau_fb;
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@ -577,7 +577,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
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struct drm_nouveau_gem_pushbuf_bo *bo;
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struct nouveau_channel *chan;
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struct validate_op op;
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struct nouveau_fence *fence = 0;
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struct nouveau_fence *fence = NULL;
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int i, j, ret = 0, do_reloc = 0;
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NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
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@ -371,7 +371,7 @@ nouveau_mem_detect(struct drm_device *dev)
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} else {
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dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA);
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dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
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dev_priv->vram_size &= 0xffffffff00;
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dev_priv->vram_size &= 0xffffffff00ll;
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if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) {
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dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
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dev_priv->vram_sys_base <<= 12;
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@ -112,6 +112,12 @@ nv04_fifo_channel_id(struct drm_device *dev)
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NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
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}
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#ifdef __BIG_ENDIAN
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#define DMA_FETCH_ENDIANNESS NV_PFIFO_CACHE1_BIG_ENDIAN
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#else
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#define DMA_FETCH_ENDIANNESS 0
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#endif
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int
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nv04_fifo_create_context(struct nouveau_channel *chan)
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{
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@ -138,10 +144,7 @@ nv04_fifo_create_context(struct nouveau_channel *chan)
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RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
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NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
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#ifdef __BIG_ENDIAN
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NV_PFIFO_CACHE1_BIG_ENDIAN |
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#endif
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0));
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DMA_FETCH_ENDIANNESS));
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dev_priv->engine.instmem.finish_access(dev);
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/* enable the fifo dma operation */
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@ -342,7 +342,7 @@ static uint32_t nv04_graph_ctx_regs[] = {
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};
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struct graph_state {
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int nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
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uint32_t nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
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};
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struct nouveau_channel *
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@ -212,7 +212,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
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struct nouveau_gpuobj *ctx;
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struct nouveau_gpuobj *obj;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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int hdr, ret;
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@ -223,7 +223,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
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NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
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if (ret)
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return ret;
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ctx = chan->ramin_grctx->gpuobj;
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obj = chan->ramin_grctx->gpuobj;
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hdr = IS_G80 ? 0x200 : 0x20;
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dev_priv->engine.instmem.prepare_access(dev, true);
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@ -241,12 +241,12 @@ nv50_graph_create_context(struct nouveau_channel *chan)
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struct nouveau_grctx ctx = {};
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = chan->ramin_grctx->gpuobj;
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ctx.data = obj;
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nv50_grctx_init(&ctx);
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} else {
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nouveau_grctx_vals_load(dev, ctx);
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nouveau_grctx_vals_load(dev, obj);
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}
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nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12);
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nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12);
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dev_priv->engine.instmem.finish_access(dev);
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return 0;
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