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phy: miphy365x: Provide support for the MiPHY356x Generic PHY
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
parent
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commit
6e877fedb1
3 changed files with 627 additions and 0 deletions
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@ -38,6 +38,16 @@ config PHY_MVEBU_SATA
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depends on OF
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select GENERIC_PHY
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config PHY_MIPHY365X
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tristate "STMicroelectronics MIPHY365X PHY driver for STiH41x series"
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depends on ARCH_STI
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depends on GENERIC_PHY
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depends on HAS_IOMEM
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depends on OF
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help
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Enable this to support the miphy transceiver (for SATA/PCIE)
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that is part of STMicroelectronics STiH41x SoC series.
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config OMAP_CONTROL_PHY
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tristate "OMAP CONTROL PHY Driver"
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depends on ARCH_OMAP2PLUS || COMPILE_TEST
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@ -8,6 +8,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
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obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
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obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
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obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
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obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o
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obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
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obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
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obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
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616
drivers/phy/phy-miphy365x.c
Normal file
616
drivers/phy/phy-miphy365x.c
Normal file
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@ -0,0 +1,616 @@
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/*
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* Copyright (C) 2014 STMicroelectronics – All Rights Reserved
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*
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* STMicroelectronics PHY driver MiPHY365 (for SoC STiH416).
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*
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* Authors: Alexandre Torgue <alexandre.torgue@st.com>
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* Lee Jones <lee.jones@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/clk.h>
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#include <linux/phy/phy.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <dt-bindings/phy/phy-miphy365x.h>
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#define HFC_TIMEOUT 100
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#define SYSCFG_2521 0x824
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#define SYSCFG_2522 0x828
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#define SYSCFG_PCIE_SATA_MASK BIT(1)
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#define SYSCFG_PCIE_SATA_POS 1
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/* MiPHY365x register definitions */
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#define RESET_REG 0x00
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#define RST_PLL BIT(1)
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#define RST_PLL_CAL BIT(2)
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#define RST_RX BIT(4)
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#define RST_MACRO BIT(7)
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#define STATUS_REG 0x01
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#define IDLL_RDY BIT(0)
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#define PLL_RDY BIT(1)
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#define DES_BIT_LOCK BIT(2)
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#define DES_SYMBOL_LOCK BIT(3)
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#define CTRL_REG 0x02
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#define TERM_EN BIT(0)
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#define PCI_EN BIT(2)
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#define DES_BIT_LOCK_EN BIT(3)
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#define TX_POL BIT(5)
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#define INT_CTRL_REG 0x03
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#define BOUNDARY1_REG 0x10
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#define SPDSEL_SEL BIT(0)
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#define BOUNDARY3_REG 0x12
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#define TX_SPDSEL_GEN1_VAL 0
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#define TX_SPDSEL_GEN2_VAL 0x01
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#define TX_SPDSEL_GEN3_VAL 0x02
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#define RX_SPDSEL_GEN1_VAL 0
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#define RX_SPDSEL_GEN2_VAL (0x01 << 3)
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#define RX_SPDSEL_GEN3_VAL (0x02 << 3)
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#define PCIE_REG 0x16
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#define BUF_SEL_REG 0x20
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#define CONF_GEN_SEL_GEN3 0x02
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#define CONF_GEN_SEL_GEN2 0x01
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#define PD_VDDTFILTER BIT(4)
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#define TXBUF1_REG 0x21
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#define SWING_VAL 0x04
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#define SWING_VAL_GEN1 0x03
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#define PREEMPH_VAL (0x3 << 5)
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#define TXBUF2_REG 0x22
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#define TXSLEW_VAL 0x2
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#define TXSLEW_VAL_GEN1 0x4
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#define RXBUF_OFFSET_CTRL_REG 0x23
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#define RXBUF_REG 0x25
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#define SDTHRES_VAL 0x01
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#define EQ_ON3 (0x03 << 4)
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#define EQ_ON1 (0x01 << 4)
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#define COMP_CTRL1_REG 0x40
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#define START_COMSR BIT(0)
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#define START_COMZC BIT(1)
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#define COMSR_DONE BIT(2)
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#define COMZC_DONE BIT(3)
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#define COMP_AUTO_LOAD BIT(4)
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#define COMP_CTRL2_REG 0x41
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#define COMP_2MHZ_RAT_GEN1 0x1e
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#define COMP_2MHZ_RAT 0xf
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#define COMP_CTRL3_REG 0x42
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#define COMSR_COMP_REF 0x33
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#define COMP_IDLL_REG 0x47
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#define COMZC_IDLL 0x2a
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#define PLL_CTRL1_REG 0x50
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#define PLL_START_CAL BIT(0)
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#define BUF_EN BIT(2)
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#define SYNCHRO_TX BIT(3)
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#define SSC_EN BIT(6)
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#define CONFIG_PLL BIT(7)
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#define PLL_CTRL2_REG 0x51
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#define BYPASS_PLL_CAL BIT(1)
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#define PLL_RAT_REG 0x52
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#define PLL_SSC_STEP_MSB_REG 0x56
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#define PLL_SSC_STEP_MSB_VAL 0x03
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#define PLL_SSC_STEP_LSB_REG 0x57
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#define PLL_SSC_STEP_LSB_VAL 0x63
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#define PLL_SSC_PER_MSB_REG 0x58
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#define PLL_SSC_PER_MSB_VAL 0
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#define PLL_SSC_PER_LSB_REG 0x59
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#define PLL_SSC_PER_LSB_VAL 0xf1
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#define IDLL_TEST_REG 0x72
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#define START_CLK_HF BIT(6)
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#define DES_BITLOCK_REG 0x86
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#define BIT_LOCK_LEVEL 0x01
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#define BIT_LOCK_CNT_512 (0x03 << 5)
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static u8 ports[] = { MIPHY_PORT_0, MIPHY_PORT_1 };
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struct miphy365x_phy {
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struct phy *phy;
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void __iomem *base;
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void __iomem *sata;
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void __iomem *pcie;
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u8 type;
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u8 port;
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};
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struct miphy365x_dev {
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struct device *dev;
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struct regmap *regmap;
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struct mutex miphy_mutex;
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struct miphy365x phys[ARRAY_SIZE(ports)];
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bool pcie_tx_pol_inv;
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bool sata_tx_pol_inv;
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u32 sata_gen;
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};
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/*
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* These values are represented in Device tree. They are considered to be ABI
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* and although they can be extended any existing values must not change.
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*/
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enum miphy_sata_gen {
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SATA_GEN1 = 1,
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SATA_GEN2,
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SATA_GEN3
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};
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static u8 rx_tx_spd[] = {
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TX_SPDSEL_GEN1_VAL | RX_SPDSEL_GEN1_VAL,
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TX_SPDSEL_GEN2_VAL | RX_SPDSEL_GEN2_VAL,
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TX_SPDSEL_GEN3_VAL | RX_SPDSEL_GEN3_VAL
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};
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/*
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* This function selects the system configuration,
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* either two SATA, one SATA and one PCIe, or two PCIe lanes.
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*/
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static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
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struct miphy365x_dev *miphy_dev)
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{
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u8 config = miphy_phy->type | miphy_phy->port;
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u32 mask = SYSCFG_PCIE_SATA_MASK;
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u32 reg;
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bool sata;
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switch (config) {
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case MIPHY_SATA_PORT0:
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reg = SYSCFG_2521;
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sata = true;
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break;
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case MIPHY_PCIE_PORT1:
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reg = SYSCFG_2522;
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sata = false;
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break;
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default:
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dev_err(miphy_dev->dev, "Configuration not supported\n");
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return -EINVAL;
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}
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return regmap_update_bits(miphy_dev->regmap, reg, mask,
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sata << SYSCFG_PCIE_SATA_POS);
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}
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static int miphy365x_init_pcie_port(struct miphy365x_phy *miphy_phy,
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struct miphy365x_dev *miphy_dev)
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{
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u8 val;
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if (miphy_phy->pcie_tx_pol_inv) {
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/* Invert Tx polarity and clear pci_txdetect_pol bit */
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val = TERM_EN | PCI_EN | DES_BIT_LOCK_EN | TX_POL;
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writeb_relaxed(val, miphy_phy->base + CTRL_REG);
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writeb_relaxed(0x00, miphy_phy->base + PCIE_REG);
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}
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return 0;
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}
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static inline int miphy365x_hfc_not_rdy(struct miphy365x_phy *miphy_phy,
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struct miphy365x_dev *miphy_dev)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
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u8 mask = IDLL_RDY | PLL_RDY;
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u8 regval;
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do {
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regval = readb_relaxed(miphy_phy->base + STATUS_REG);
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if (!(regval & mask))
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return 0;
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usleep_range(2000, 2500);
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} while (time_before(jiffies, timeout));
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dev_err(miphy_dev->dev, "HFC ready timeout!\n");
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return -EBUSY;
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}
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static inline int miphy365x_rdy(struct miphy365x_phy *miphy_phy,
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struct miphy365x_dev *miphy_dev)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(HFC_TIMEOUT);
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u8 mask = IDLL_RDY | PLL_RDY;
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u8 regval;
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do {
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regval = readb_relaxed(miphy_phy->base + STATUS_REG);
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if ((regval & mask) == mask)
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return 0;
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usleep_range(2000, 2500);
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} while (time_before(jiffies, timeout));
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dev_err(miphy_dev->dev, "PHY not ready timeout!\n");
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return -EBUSY;
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}
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static inline void miphy365x_set_comp(struct miphy365x_phy *miphy_phy,
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struct miphy365x_dev *miphy_dev)
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{
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u8 val, mask;
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if (miphy_dev->sata_gen == SATA_GEN1)
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writeb_relaxed(COMP_2MHZ_RAT_GEN1,
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miphy_phy->base + COMP_CTRL2_REG);
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else
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writeb_relaxed(COMP_2MHZ_RAT,
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miphy_phy->base + COMP_CTRL2_REG);
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if (miphy_dev->sata_gen != SATA_GEN3) {
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writeb_relaxed(COMSR_COMP_REF,
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miphy_phy->base + COMP_CTRL3_REG);
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/*
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* Force VCO current to value defined by address 0x5A
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* and disable PCIe100Mref bit
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* Enable auto load compensation for pll_i_bias
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*/
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writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG);
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writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG);
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}
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/*
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* Force restart compensation and enable auto load
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* for Comzc_Tx, Comzc_Rx and Comsr on macro
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*/
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val = START_COMSR | START_COMZC | COMP_AUTO_LOAD;
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writeb_relaxed(val, miphy_phy->base + COMP_CTRL1_REG);
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mask = COMSR_DONE | COMZC_DONE;
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while ((readb_relaxed(miphy_phy->base + COMP_CTRL1_REG) & mask) != mask)
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cpu_relax();
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}
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static inline void miphy365x_set_ssc(struct miphy365x_phy *miphy_phy,
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struct miphy365x_dev *miphy_dev)
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{
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u8 val;
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/*
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* SSC Settings. SSC will be enabled through Link
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* SSC Ampl. = 0.4%
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* SSC Freq = 31KHz
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*/
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writeb_relaxed(PLL_SSC_STEP_MSB_VAL,
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miphy_phy->base + PLL_SSC_STEP_MSB_REG);
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writeb_relaxed(PLL_SSC_STEP_LSB_VAL,
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miphy_phy->base + PLL_SSC_STEP_LSB_REG);
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writeb_relaxed(PLL_SSC_PER_MSB_VAL,
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miphy_phy->base + PLL_SSC_PER_MSB_REG);
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writeb_relaxed(PLL_SSC_PER_LSB_VAL,
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miphy_phy->base + PLL_SSC_PER_LSB_REG);
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/* SSC Settings complete */
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if (miphy_dev->sata_gen == SATA_GEN1) {
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val = PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
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writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
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} else {
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val = SSC_EN | PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
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writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
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}
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}
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static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
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struct miphy365x_dev *miphy_dev)
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{
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int ret;
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u8 val;
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/*
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* Force PHY macro reset, PLL calibration reset, PLL reset
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* and assert Deserializer Reset
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*/
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val = RST_PLL | RST_PLL_CAL | RST_RX | RST_MACRO;
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writeb_relaxed(val, miphy_phy->base + RESET_REG);
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if (miphy_dev->sata_tx_pol_inv)
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writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);
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/*
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* Force macro1 to use rx_lspd, tx_lspd
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* Force Rx_Clock on first I-DLL phase
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* Force Des in HP mode on macro, rx_lspd, tx_lspd for Gen2/3
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*/
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writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);
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writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);
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val = rx_tx_spd[miphy_dev->sata_gen];
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writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);
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/* Wait for HFC_READY = 0 */
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ret = miphy365x_hfc_not_rdy(miphy_phy, miphy_dev);
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if (ret)
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return ret;
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/* Compensation Recalibration */
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miphy365x_set_comp(miphy_phy, miphy_dev);
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switch (miphy_dev->sata_gen) {
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case SATA_GEN3:
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/*
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* TX Swing target 550-600mv peak to peak diff
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* Tx Slew target 90-110ps rising/falling time
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* Rx Eq ON3, Sigdet threshold SDTH1
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*/
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val = PD_VDDTFILTER | CONF_GEN_SEL_GEN3;
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writeb_relaxed(val, miphy_phy->base + BUF_SEL_REG);
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val = SWING_VAL | PREEMPH_VAL;
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writeb_relaxed(val, miphy_phy->base + TXBUF1_REG);
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writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
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writeb_relaxed(0x00, miphy_phy->base + RXBUF_OFFSET_CTRL_REG);
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val = SDTHRES_VAL | EQ_ON3;
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writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
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break;
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case SATA_GEN2:
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/*
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* conf gen sel=0x1 to program Gen2 banked registers
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* VDDT filter ON
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* Tx Swing target 550-600mV peak-to-peak diff
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* Tx Slew target 90-110 ps rising/falling time
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* RX Equalization ON1, Sigdet threshold SDTH1
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*/
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writeb_relaxed(CONF_GEN_SEL_GEN2,
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miphy_phy->base + BUF_SEL_REG);
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writeb_relaxed(SWING_VAL, miphy_phy->base + TXBUF1_REG);
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writeb_relaxed(TXSLEW_VAL, miphy_phy->base + TXBUF2_REG);
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val = SDTHRES_VAL | EQ_ON1;
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writeb_relaxed(val, miphy_phy->base + RXBUF_REG);
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break;
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case SATA_GEN1:
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/*
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* conf gen sel = 00b to program Gen1 banked registers
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* VDDT filter ON
|
||||
* Tx Swing target 500-550mV peak-to-peak diff
|
||||
* Tx Slew target120-140 ps rising/falling time
|
||||
*/
|
||||
writeb_relaxed(PD_VDDTFILTER, miphy_phy->base + BUF_SEL_REG);
|
||||
writeb_relaxed(SWING_VAL_GEN1, miphy_phy->base + TXBUF1_REG);
|
||||
writeb_relaxed(TXSLEW_VAL_GEN1, miphy_phy->base + TXBUF2_REG);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Force Macro1 in partial mode & release pll cal reset */
|
||||
writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
|
||||
usleep_range(100, 150);
|
||||
|
||||
miphy365x_set_ssc(miphy_phy, miphy_dev);
|
||||
|
||||
/* Wait for phy_ready */
|
||||
ret = miphy365x_rdy(miphy_phy, miphy_dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Enable macro1 to use rx_lspd & tx_lspd
|
||||
* Release Rx_Clock on first I-DLL phase on macro1
|
||||
* Assert deserializer reset
|
||||
* des_bit_lock_en is set
|
||||
* bit lock detection strength
|
||||
* Deassert deserializer reset
|
||||
*/
|
||||
writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);
|
||||
writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);
|
||||
writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
|
||||
val = miphy_dev->sata_tx_pol_inv ?
|
||||
(TX_POL | DES_BIT_LOCK_EN) : DES_BIT_LOCK_EN;
|
||||
writeb_relaxed(val, miphy_phy->base + CTRL_REG);
|
||||
|
||||
val = BIT_LOCK_CNT_512 | BIT_LOCK_LEVEL;
|
||||
writeb_relaxed(val, miphy_phy->base + DES_BITLOCK_REG);
|
||||
writeb_relaxed(0x00, miphy_phy->base + RESET_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int miphy365x_init(struct phy *phy)
|
||||
{
|
||||
struct miphy365x_phy *miphy_phy = phy_get_drvdata(phy);
|
||||
struct miphy365x_dev *miphy_dev = dev_get_drvdata(phy->dev.parent);
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock(&miphy_dev->miphy_mutex);
|
||||
|
||||
ret = miphy365x_set_path(miphy_phy, miphy_dev);
|
||||
if (ret) {
|
||||
mutex_unlock(&miphy_dev->miphy_mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Initialise Miphy for PCIe or SATA */
|
||||
if (miphy_phy->type == MIPHY_TYPE_PCIE)
|
||||
ret = miphy365x_init_pcie_port(miphy_phy, miphy_dev);
|
||||
else
|
||||
ret = miphy365x_init_sata_port(miphy_phy, miphy_dev);
|
||||
|
||||
mutex_unlock(&miphy_dev->miphy_mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct phy *miphy365x_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct miphy365x_dev *state = dev_get_drvdata(dev);
|
||||
u8 port, type;
|
||||
|
||||
if (args->count != 2) {
|
||||
dev_err(dev, "Invalid number of cells in 'phy' property\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (args->args[0] & 0xFFFFFF00 || args->args[1] & 0xFFFFFF00) {
|
||||
dev_err(dev, "Unsupported flags set in 'phy' property\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
port = args->args[0];
|
||||
type = args->args[1];
|
||||
|
||||
if (WARN_ON(port >= ARRAY_SIZE(ports)))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
if (type == MIPHY_TYPE_SATA)
|
||||
state->phys[port].base = state->phys[port].sata;
|
||||
else if (type == MIPHY_TYPE_PCIE)
|
||||
state->phys[port].base = state->phys[port].pcie;
|
||||
else {
|
||||
WARN(1, "Invalid type specified in DT");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
state->phys[port].type = type;
|
||||
|
||||
return state->phys[port].phy;
|
||||
}
|
||||
|
||||
static struct phy_ops miphy365x_ops = {
|
||||
.init = miphy365x_init,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static int miphy365x_get_base_addr(struct platform_device *pdev,
|
||||
struct miphy365x_phy *phy, u8 port)
|
||||
{
|
||||
struct resource *res;
|
||||
char type[6];
|
||||
|
||||
sprintf(type, "sata%d", port);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, type);
|
||||
phy->sata = devm_ioremap_resource(&pdev->dev, res));
|
||||
if (!phy->sata)
|
||||
return -ENOMEM;
|
||||
|
||||
sprintf(type, "pcie%d", port);
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, type);
|
||||
phy->pcie = devm_ioremap_resource(&pdev->dev, res));
|
||||
if (!phy->pcie)
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int miphy365x_of_probe(struct device_node *np,
|
||||
struct miphy365x_dev *phy_dev)
|
||||
{
|
||||
phy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
|
||||
if (IS_ERR(phy_dev->regmap)) {
|
||||
dev_err(phy_dev->dev, "No syscfg phandle specified\n");
|
||||
return PTR_ERR(phy_dev->regmap);
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "st,sata-gen", &phy_dev->sata_gen);
|
||||
if (!phy_dev->sata_gen)
|
||||
phy_dev->sata_gen = SATA_GEN1;
|
||||
|
||||
phy_dev->pcie_tx_pol_inv =
|
||||
of_property_read_bool(np, "st,pcie-tx-pol-inv");
|
||||
|
||||
phy_dev->sata_tx_pol_inv =
|
||||
of_property_read_bool(np, "st,sata-tx-pol-inv");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int miphy365x_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct miphy365x_dev *phy_dev;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct phy_provider *provider;
|
||||
u8 port;
|
||||
int ret;
|
||||
|
||||
phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
|
||||
if (!phy_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = miphy365x_of_probe(np, phy_dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
phy_dev->dev = dev;
|
||||
|
||||
dev_set_drvdata(dev, phy_dev);
|
||||
|
||||
mutex_init(&phy_dev->miphy_mutex);
|
||||
|
||||
for (port = 0; port < ARRAY_SIZE(ports); port++) {
|
||||
struct phy *phy;
|
||||
|
||||
phy = devm_phy_create(dev, &miphy365x_ops, NULL);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "failed to create PHY on port %d\n", port);
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
|
||||
phy_dev->phys[port].phy = phy;
|
||||
phy_dev->phys[port].port = port;
|
||||
|
||||
ret = miphy365x_get_base_addr(pdev,
|
||||
&phy_dev->phys[port], port);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
phy_set_drvdata(phy, &phy_dev->phys[port]);
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, miphy365x_xlate);
|
||||
if (IS_ERR(provider))
|
||||
return PTR_ERR(provider);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id miphy365x_of_match[] = {
|
||||
{ .compatible = "st,miphy365x-phy", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, miphy365x_of_match);
|
||||
|
||||
static struct platform_driver miphy365x_driver = {
|
||||
.probe = miphy365x_probe,
|
||||
.driver = {
|
||||
.name = "miphy365x-phy",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = miphy365x_of_match,
|
||||
}
|
||||
};
|
||||
module_platform_driver(miphy365x_driver);
|
||||
|
||||
MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
|
||||
MODULE_DESCRIPTION("STMicroelectronics miphy365x driver");
|
||||
MODULE_LICENSE("GPL v2");
|
Loading…
Reference in a new issue